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? 2016 microchip technology inc. ds00002112a-page 1 target applications industrial etherne t applications that employ ieee 802.3-compliant macs. (ethernet/ip, profinet, modbus tcp, etc.) voip phone set-top/game box automotive industrial control iptv pof soho residential gateway with full-wire speed of four lan ports broadband gateway/firewall/vpn integrated dsl/cable modem wireless lan access point + gateway standalone 10/100 switch networked measurement and control systems features management capabilities - the KSZ8795clx includes all the functions of a 10/100base-t/tx sw itch system which combines a switch engine, frame buffer management, address look-up table, queue management, mib counters, media access controllers (mac), and phy trans- ceivers - non-blocking store-and-forward switch fabric assures fast packet delivery by uti- lizing a 1024-entries forwarding table - port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port - mib counters for fully-compliant statistics gathering (36 counters per port) - support hardware for port-based flush and freeze command in mib counter. - multiple loopback of remote, phy, and mac modes support for the diagnostics - rapid spanning tree support (rstp) for topology management and ring/linear recovery robust phy ports - four integrated ieee 802.3/802.3u-compli- ant ethernet transceivers supporting 10base-t and 100base-tx - - 802.1az eee supported - on-chip termination resistors and internal biasing for differential pairs to reduce power - hp auto mdi/mdi-x crossover support elim- inates the need to differentiate between straight or crossover cables in applications mac and gmac ports - four internal media access control (mac1 to mac4) units and one internal gigabit media access control (gmac5) unit - gmii, rgmii, mii or rmii interfaces support for the port 5 gmac5 with uplink - 2 kbyte jumbo packet support - tail tagging mode (one byte added before fcs) support on port 5 to inform the proces- sor in which the ingress port receives the packet and its priority - supports reduced media independent inter- face (rmii) with 50 mhz reference clock output - supports media independent interface (mii) in either phy mode or mac mode on port 5 - linkmd ? cable diagnostic capabilities for determining cable opens, shorts, and length advanced switch capabilities - non-blocking store-and-forward switch fabric assures fast packet delivery by uti- lizing 1024 entry forwarding table - 64 kb frame buffer ram - ieee 802.1q vlan support for up to 128 active vlan groups (full-range 4096 of vlan ids) - ieee 802.1p/q tag insertion or removal on a per port basis (egress) - vlan id tag/untag options on per port basis - fully compliant wi th ieee 8 02.3/802.3u standards - ieee 802.3x full-duplex with force-mode option and half-duplex back-pressure colli- sion flow control - ieee 802.1w rapid spanning tree protocol support KSZ8795clx integrated 5-port 10/100-managed ethernet switch with gigabit gmii/rgmii and mii/ rmii interfaces downloaded from: http:///
KSZ8795clx ? 2016 microchip technology inc. ds00002112a-page 2 - igmp v1/v2/v3 snooping for multicast packet filtering - qos/cos packets prio ritization support: 802.1p, diffserv-based and re-mapping of 802.1p priority field per port basis on four priority levels - ipv4/ipv6 qos support - ipv6 multicast listener discovery (mld) snooping - programmable rate limiting at the ingress and egress ports on a per port basis - jitter-free per packet based rate limiting support - tail tag mode (1 byte added before fcs) support on port 5 to inform the processor which ingress port receives the packet - broadcast storm protection with percentage control (global and per port basis) - 1k entry forwarding table with 64 kb frame buffer - 4 priority queues with dynamic packet map- ping for ieee 802.1p, ipv4 tos (diff- serv), ipv6 traffic class, etc. - supports wol using amds magic packet - vlan and address filtering - supports 802.1x port-based security, authentication and mac-based authentica- tion via access control lists (acl) - provides port-based and rule-based acls to support layer 2 mac sa/da address, layer 3 ip address and ip mask, layer 4 tcp/udp port number , ip protocol, tcp flag and compensation for the port security filtering - ingress and egress rate limit based on bit per second (bps) and packet-based rate limiting (pps) configuration registers access - high-speed spi (4-wire, up to 50 mhz) inter- face to access all internal registers - mii management (miim, mdc/mdio 2-wire) interface to access al l phy registers per clause 22.2.4.5 of the ieee 802.3 specifica- tion - i/o pin strapping facility to set certain reg- ister bits from i/o pins during reset time - control registers configurable on-the-fly power and power management - full-chip software power-down (all register values are not saved and strap-in value will re-strap after it releases the power-down) - per-port software power-down - energy detect power-down (edpd), which disables the phy transceiver when cables are removed - supports ieee p802.3az energy efficient ethernet (eee) to reduce power consump- tion in transceivers in lpi state even though cables are not removed - dynamic clock tree control to reduce clocking in areas that are not in use - low power consumption without extra power consumption on transformers - voltages: using external ldo power sup- plies - analog v ddat 3.3v or 2.5v -v ddio support 3.3v, 2.5v, and 1.8v - low 1.2v voltage for analog and digital core power - wol support with configurable packet con- trol additional features - single 25 mhz +50 ppm reference clock requirement - comprehensive programmable two-led indicator support for link, activity, full-/half- duplex, and 10/100 speed packaging and environmental - commercial temperature range: 0c to +70c - industrial temperature range: C40c to +85c - package available in an 80-pin lqfp, lead- free (rohs-compliant) package - supports human body model (hbm) esd rating of 5 kv - 0.065 m cmos technology for lower power consumption downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 3 KSZ8795clx to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our public ations to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing co mmunications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data s heet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the version number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operati onal differences from the data sheet and recommended workarounds, may exist for cur- rent devices. as device/doc umentation issues become known to us, we will publish an errata s heet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particul ar device, please check with one of the following: microchips worldwide web site; http://www.microchip.com your local microchip sales office (see last page) when contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) yo u are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. downloaded from: http:///
KSZ8795clx ds00002112a-page 4 ? 2016 microchip technology inc. table of contents 1.0 introduction ..................................................................................................................................................................................... 5 2.0 pin description and configuration ................................................................................................................................................... 6 3.0 functional description .................................................................................................... ............................................................... 13 4.0 device registers ........................................................................................................................................................................... 46 5.0 operational characteristics ............................................................................................... .......................................................... 112 6.0 electrical characteristics ................................................................................................ ............................................................. 113 7.0 timing diagrams .......................................................................................................................................................................... 115 8.0 reset circuit.............................................................................................................. ................................................................... 125 9.0 selection of isolation transformer ......................................................................................... ...................................................... 126 10.0 selection of reference crystal............................................................................................ ....................................................... 126 11.0 package outlines .......................................................................................................... ............................................................. 127 appendix a: data sheet revision history ....................................................................................... .................................................. 128 the microchip web site ........................................................................................................ ............................................................ 129 customer change notification service ............................................................................................................................................. 129 product identification system ................................................................................................. ........................................................... 130 customer support ............................................................................................................................................................................. 132 downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 5 KSZ8795clx 1.0 introduction 1.1 general description the KSZ8795clx is a highly integrated, layer 2-managed, 5-port switch with numerous features designed to reduce system cost. it is inten ded for cost-sensitive applications requiring four 10/100 mbps copper ports and one 10/100/ 1000 mbps gigabit uplink port. the KSZ8795clx incorporates a small package outline, lowest power consumption with internal biasing, and on-chip termination. its extensive features set includes enhan ced power management, program- mable rate limiting and priority ratio, tagged and port-bas ed vlan, port-based security and acl rule-based packet fil- tering technology, quality-of-service (qos) priority with four queues, management interf aces, enhanced mib counters, high-performance memory bandwidth, and a shared memory- based switch fabric with non-blocking support. the KSZ8795clx provides support for multiple cpu data interfaces to effectively address both current and emerging fast ethernet and gigabit ethernet applications where the port 5 gmac can be configured to any of gmii, rgmii, mii and rmii modes. the KSZ8795clx is built upon industry-leading ethernet ana log and digital technology, with features designed to off- load host processing and streamline the overall design. four integrated 10/100base-t/tx mac/phys one integrated 10/100/1000base-t/ tx gmac with selectable gmii, rgmii, mii, and rmii interfaces small 80-pin lqfp package a robust assortment of power-manageme nt features including energy effici ent ethernet (eee), pme, and wake-on- lan (wol) have been designed-in to satisfy energy-efficient environments. KSZ8795clx supports two management inte rface modes of spi and miim only, spi access all registers, miim mode access all phys registers through mdc/mdio interface. figure 1-1: functional block diagram auto mdi/mdix auto mdi/mdix auto mdi/mdix auto mdi/mdix sw5-gmii/rgmii/mii/rmii mdc, mdi/o for miim control reg spi i/f led0 [4:1]led1 [4:1] KSZ8795 10/100 t/tx eee phy1 10/100 t/tx eee phy2 10/100 t/tx eee phy3 10/100 t/tx eee phy4 led i/f 10/100 mac 1 10/100 mac 2 10/100 mac 3 10/100 mac 4 10/100/1000 gmac 5 spi control registers 1k look-up engine queue management buffer management frame buffer mib counters fifo, flow control, vlan tagging, priority downloaded from: http:///
KSZ8795clx ds00002112a-page 6 ? 2016 microchip technology inc. 2.0 pin description and configuration figure 2-1: 80-lqfp pin assignment (top view) xoxi gnda iset vddat33 atst nc vdd12d rst_n gndd vddio spis_n sda_mdio scl_mdc spiq led1_0 led1_1 led2_0 led2_1 gndd gnda nc intr_n led3_1led3_0 vdd12d gndd led4_1 txen5/txds5_ctl txd5_0 led4_0 txd5_1 gndd vddio txd5_2txd5_3 txer5 txd5_4txd5_5 txd5_6 6059 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 rxd5_7rxd5_6 rxd5_5 rxd5_4 pme refclko col5 crs5 rxer5 rxdv5/crsdv5/rxd5_ctl rxd5_3 rxd5_2 vddio gndd rxd5_1 rxd5_0 rxc5/grxc5 txc5/refclki5/gtxc5 vdd12d txd5_7 6162 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 2122 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 vdd12a vddat33 gnda rxp1 rxm1 txp1 txm1 rxp2 rxm2 txp2 txm2 vddat33 rxp3 rxm3 txp3 txm3 rxp4 rxm4 txp4 txm4 KSZ8795 (top view) downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 7 KSZ8795clx table 2-1: signals - KSZ8795clx pin number pin name type note 2-1 port description 1 vdd12a p 1.2v core power 2 vddat p 3.3v or 2.5v analog power. 3 gnda gnd analog ground. 4 rxp1 i 1 port 1 physical receiv e signal + (differential). 5 rxm1 i 1 port 1 physical receive signal - (differential). 6 txp1 o 1 port 1 physical transmit signal + (differential). 7 txm1 o 1 port 1 physical transmit signal - (differential). 8 rxp2 i 2 port 2 physical receiv e signal + (differential). 9 rxm2 i 2 port 2 physical receive signal - (differential). 10 txp2 o 2 port 2 physi cal transmit signal + (differential). 11 txm2 o 2 port 2 physical transmit signal - (differential). 12 vddat p 3.3v or 2.5v analog power. 13 rxp3 i 3 port 3 physical receiv e signal + (differential). 14 rxm3 i 3 port 3 physical receive signal - (differential). 15 txp3 o 3 port 3 physi cal transmit signal + (differential). 16 txm3 o 3 port 3 physical transmit signal C (differential). 17 rxp4 i 4 port 4 physical receiv e signal + (differential). 18 rxm4 i 4 port 4 physical receive signal - (differential). 19 txp4 o 4 port 4 physi cal transmit signal + (differential). 20 txm4 o 4 port 4 physical transmit signal - (differential). 21 gnda gnd analog ground. 22 nc nc no connect. 23 intr_n opu interrupt: active-low. this pin is open-drain output pin. note : an external pull-up resistor is needed on this pin when it is in use. 24 led3_1 ipu/o 3 port 3 led indicator 1: see global register 11 bits [5:4] for details. strap option: switch port 5 gmac5 interface mode select by led3[1:0] 00 = mii for sw5-mii 01 = rmii for sw5-rmii 10 = gmii for sw5-gmii 11 = rgmii for sw5-rgmii (default) 25 led3_0 ipu/o 3 port 3 led indicator 0: see global register 11 bits [5:4] for details. strap option: see led3_1. downloaded from: http:///
KSZ8795clx ds00002112a-page 8 ? 2016 microchip technology inc. 26 vdd12d p 1.2v core power. 27 gndd gnd digital ground. 28 led4_1 ipu/o 4 port 4 led indicator 1: see global register 11 bits [5:4] for details. 29 txen5/ txd5_ctl ipd 5 gmii/mii/rmii: port 5 switch transmit enable. rgmii: transmit data control. 30 txd5_0 ipd 5 gmii/rgmii/mii/rmii: po rt 5 switch tr ansmit bit[0]. 31 led4_0 ipu/o 4 port 4 led indicator 0: see global register 11 bits [5:4] for details. 32 txd5_1 ipd 5 gmii/rgmii/mii/rmii: po rt 5 switch tr ansmit bit[1]. 33 gndd gnd digital ground. 34 vddio p 3.3v, 2.5v, or 1.8v digital vdd for digital i/o circuitry. 35 txd5_2 ipd 5 gmii/rgmii/mii: po rt 5 switch transmit bit[2]. rmii: no connection. 36 txd5_3 ipd 5 gmii/rgmii/mii: po rt 5 switch transmit bit[3]. rmii: no connection. 37 txer5 ipd 5 gmii/mii: port 5 switch transmit error. rgmii/rmii: no connection. 38 txd5_4 ipd 5 gmii: port 5 switch transmit bit[4]. rgmii/mii/rmii: no connection. 39 txd5_5 ipd 5 gmii: port 5 switch transmit bit[5]. rgmii/mii/rmii: no connection. 40 txd5_6 ipd 5 gmii: port 5 switch transmit bit[6]. rgmii/mii/rmii: no connection. 41 txd5_7 ipd 5 gmii: port 5 switch transmit bit[7]. rgmii/mii/rmii: no connection. 42 vdd12d p 1.2v core power. 43 txc5/ refclki/ gtxc5 i/o 5 port 5 switch gmac5 clock pin: mii: 2.5/25 mhz clock, phy mode is output, mac mode is input. rmii: input for receiving 50 mhz clock in normal mode gmii: input 125 mhz clock for the transmit rgmii: input 125 mhz clock with falling and rising edge to latch data for the transmit. 44 rxc5/ grxc5 i/o 5 port 5 switch gmac5 clock pin: mii: 2.5/25 mhz clock, phy mode is output, mac mode is input. rmii: output 50 mhz reference cl ock for the receiving/transmit in the clock mode. gmii: output 125 mhz clock for the receiving. rgmii: output 125 mhz clock with falling and rising edge to latch data for the receiving. table 2-1: signals - ks z8795clx (continued) pin number pin name type note 2-1 port description downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 9 KSZ8795clx 45 rxd5_0 ipd/o 5 gmii/rgmii/mii/rmii: port 5 switch receive bit[0]. 46 rxd5_1 ipd/o 5 gmii/rgmii/mii/rmii: port 5 switch receive bit[1]. 47 gndd gnd digital ground. 48 vddio p 3.3v, 2.5v, or 1.8v digital vdd for digital i/o circuitry. 49 rxd5_2 ipd/o 5 gmii/rgmii/mii: po rt 5 switch receive bit[2]. rmii: no connection 50 rxd5_3 ipd/o 5 gmii/rgmii/mii: po rt 5 switch receive bit[3]. rmii: no connection 51 rxdv5/ crsdv5/ rxd5_ctl ipd/o 5 gmii/mii: rxdv5 is for port 5 switch gmii/mii receive data valid. rmii: crsdv5 is for port 5 rmii carrier sense/receive data valid output. rgmii: rxd5_ctl is for port 5 rgmii receive data control 52 rxer5 ipd/o 5 gmii/mii: port 5 switch receive error. rgmii/rmii: no connection. 53 crs5 ipd/o 5 gmii/mii: port 5 s witch mii modes carrier sense. rgmii/rmii: no connection. 54 col5 ipd/o 5 gmii/mii: port 5 switch mii collision detect. rgmii/rmii: no connection. 55 refclko ipu/o 25 mhz clock output (option) controlled by the strap pin led2_0 and the global register 11 bit[1]. default is enabled; it is bett er to disable it if its not being used. 56 pme_n i/o power management event this output signal indicates th at a wol event has been detected as a result of a wake-up frame being detected. the KSZ8795- clx is requesting the system to wake up from low power mode. its assertion polarity is programmable with the default polarity to be active-low. 57 rxd5_4 ipd/o 5 gmii: port 5 switch receive bit[4]. rgmii/mi/rmii: no connection. 58 rxd5_5 ipd/o 5 gmii: port 5 switch receive bit[5]. rgmii/mii/rmii: no connection. 59 rxd5_6 ipd/o 5 gmii: port 5 switch receive bit[6]. rgmii/mii/rmii: no connection. 60 rxd5_7 ipd/o 5 gmii: port 5 switch receive bit[7]. rgmii/mii/rmii: no connection. 61 gndd gnd digital ground. table 2-1: signals - ks z8795clx (continued) pin number pin name type note 2-1 port description downloaded from: http:///
KSZ8795clx ds00002112a-page 10 ? 2016 microchip technology inc. 62 led2_1 ipu/o 2 port 2 led indicator 1: see global register 11 bits [5:4] for details. strap option: port 5 gmii/mii and rmii mode select when port 5 is gmii/mii mode: pu = gmii/mii is in gmac/mac mode. (default) pd = gmii/mii is in gphy/phy mode. note: when set gmac5 gmii to gphy mode, the crs and col pins will change from the input to output. when set mii to phy mode, the crs, col, rxc and txc pins will change from the input to output. when port 5 is rmii mode: pu = clock mode in rmii, using 25mhz osc clock and provide 50 mhz rmii clock from pin rxc5. pd = normal mode in rmii, the txc5/refclki5 pin on the port 5 rmii will receive an external 50 mhz clock note: port 5 also can use either an internal or external clock in rmii mode based on this strap pin or the setting of the register 86 (0x56) bit[7]. 63 led2_0 ipu/o 2 port 2 led indicator 0: see global register 11 bits [5:4] for details. strap option: refclko enable pu = refclk_o (25 mhz) is enabled. (default) pd = refclk_o is disabled. note: it is better to disable this 25 mhz clock if not providing an extra 25 mhz clock for the system. 64 led1_1 ipu/o 1 port 1 led indicator 1: see global register 11 bits [5:4] for details. strap option: pll clock source select pu = still use 25 mhz clock from xi/xo pin even though it is in port 5 rmii normal mode. pd = use external clock from pin txc5 in port 5 rmii normal mode. note: if received clock in port 5 rmii normal mode has large clock jitter, one can select the 25 mhz crystal/oscillator as the switchs clock source. 65 led1_0 ipu/o 1 port 1 led indicator 0: see global register 11 bits [5:4] for details. strap option: speed select in gmii/rgmii pu = 1gbps in gmii/rgmii.(default) pd = 10/100mbps in gmii/rgmii. note: programmable through internal registers also. 66 spiq ipd/o all spi serial data output in spi slave mode: strap option: serial bus configuration. pd = spi slave mode. pu = mdc/mdio mode. note: an external pull-up or pull-down resistor is required. 67 scl_mdc ipu all clock input for spi or mdc/mdio interface: input clock up to 50 mhz in spi slave mode. input clock up to 25 mhz in mdc/mdio for miim access. table 2-1: signals - ks z8795clx (continued) pin number pin name type note 2-1 port description downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 11 KSZ8795clx note 2-1 p = power supply; gnd = gro und; i = input; o = output i/o = bi-directional ipu = input w/internal pull-up. ipd = input w/internal pull-down. ipd/o = input w/internal pull-down during reset, output pin otherwise. ipu/o = input w/internal pull-up du ring reset, output pin otherwise. otri = output tri-stated. pu = strap pin pull-up. pd = strap pin pull-down. nc = no connect or tie-to-ground for this product. the KSZ8795clx can function as a managed switch and utilizes strap-in pins to configure the device for different modes. the strap-in pins are configured by using external pull-up/down resistors to create a high or low state on the pins which are sampled during the power-down reset or warm reset. the functions are described in following table. 68 sda_mdio ipu/o all data for spi or mdc/mdio interface: serial data input in spi slave mode. mdc/mdio interface data input/output. 69 spis_n ipu all spi slave mode chip select (active-low): spi data transfer start in spi slave mode. when spis_n is high, the KSZ8795clx is deselected and spiq is held in the high impedance state. a high-to-low transition initiates the spi data transfer. this pin is active-low. 70 vddio p 3.3v, 2.5v or 1.8v digital vdd for digital i/o circuitry. 71 gndd gnd digital ground. 72 rst_n ipu reset: this active-low signal resets the hardware in the device. see the timing requirements in this section. 73 vdd12d p 1.2v core power. 74 nc nc no connect. 75 atst nc no connect. factory test pin. 76 vddat p 3.3v or 2.5v analog power. 77 iset transmit output current set: this pin configures the physical transmit output current. it should be connected to gnd through a 12.4 k ? 1% resistor. 78 gnda gnd analog ground. 79 xi i crystal clock input/oscillator input: when using a 25 mhz crystal, this input is connected to one end of the crystal circuit. when using a 3.3v oscillator, this is the input from the oscillator. the crystal or oscillator should have a tolerance of 50 ppm. 80 xo o crystal clock output: when using a 25 mhz crystal, this output is connected to one end of the crystal circuit. table 2-1: signals - ks z8795clx (continued) pin number pin name type note 2-1 port description downloaded from: http:///
KSZ8795clx ds00002112a-page 12 ? 2016 microchip technology inc. note 2-2 ipd/o = input w/internal pull-down dur ing reset, output pin otherwise. ipu/o = input w/internal pull-up during reset, output pin otherwise. table 2-2: strap-in options - KSZ8795clx pin number pin name type ( note 2-2 ) description 24, 25 led3[1,0] ipu/o switch port 5 gmac5 in terface mode select: strap option: 00 = mii for sw5-mii 01 = rmii for sw5-rmii 10 = gmii for sw5-gmii 11 = rgmii for sw5-rgmii (default) 62 led2_1 ipu/o port 5 gmii/mii and rmii mode select: strap option: when port 5 is gmii/mii mode: pu = gmii/mii is in gmac/mac mode. (default) pd = gmii/mii is in gphy/phy mode. note: when set gmac5 gmii to gphy mode, the crs and col pins will change from the input to output. when set mii to phy mode, the crs, col, rxc and txc pins will change from the input to out- put. when port 5 is rmii mode: pu = clock mode in rmii, using 25 mhz osc clock and provide 50 mhz rmii clock from pin rxc5. pd = normal mode in rmii, the txc5/refclki5 pin on the port 5 rmii will receive an external 50 mhz clock note: port 5 also can use either an internal or external clock in rmii mode based on this strap pin or the setting of the register 86 (0x56) bit[7]. 63 led2_0 ipu/o refclko enable: strap option: pu = refclk_o (25 mhz) is enabled. (default) pd = refclk_o is disabled. 64 led1_1 ipu/o pll clock source select: strap option: pu = still use 25 mhz clock from xi/xo pin even though it is in port 5 rmii normal mode. pd = use external clock from txc5 pin in port 5 rmii normal mode. note: if received clock in port 5 rmii normal mode with bigger clock jitter, still can select to use the 25 mhz crystal/oscillator as switchs clock source. 65 led1_0 ipu/o port 5 gigabit select: strap option: pu = 1gbps in gmii/rgmii mode (default) pd = 10/100 mbps in gmii/rgmii mode. note: programmable through internal register also 66 spiq ipd/o serial bus configuration strap option: pd = spi slave mode. (default) pu = mdc/mdio mode. note: an external pull-up or pull-down resistor is requested. if the uplink port is used for the rgmii interface, spi mode is recommend for setting register 86 (0x56) bits [4:3] for rgmii v2.0; mdc/mdio mode cant set this feature. downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 13 KSZ8795clx 3.0 functional description the KSZ8795clx contains four 10/100 physical layer transc eivers, four media access control (mac) units, and one gigabit media access control (gmac) unit with an integrated layer 2-managed sw itch. the device runs in two modes. the first mode is as a four-port standalone switch and the second is as a five-port switch with fifth port that is provided through a gigabit media independent interfac e that supports gmii, rgmii, mii, and rmii. this is useful for implementing an integrated broadband router. the KSZ8795clx has the flexibility to reside in a managed mode. in a managed mode, a host processor has complete control of the KSZ8795clx via the spi bus, or the mdc/mdio interface. on the media side, the KSZ8795clx sup ports ieee 802.3 10base-t, 100base-tx on all copper po rts with auto- mdi/ mdi-x. the KSZ8795clx can be used as a fully-managed five- port switch or hooked up to a microprocessor via its sw- gmii/rgmii/mii/rmii interfaces to allow for integrating into a variety of environments. physical signal transmission and reception are enhanced thr ough the use of patented analog circuitry and dsp tech- nology that makes the design more efficient and allows for reduced power consumption and smaller die size. major enhancements from the ksz8995 and ks8895 to the ksz 8795clx include more host interface options such as the gmii and rgmii inte rfaces, power-saving features such as ieee 8 02.1az energy efficient ethernet (eee), mld snooping, wake-on-lan (wol), port-based acl filtering for t he port security, enhanced quality-of-service (qos) priority, rapid spanning tree, igmp snooping, port mirroring support, and flexible rate limiting. 3.1 physical layer (phy) 3.1.1 100base-tx transmit the 100base-tx transmit function perfo rms parallel-to-serial conversion, 4b/5 b coding, scrambling, nrz-to-nrzi con- version, and mlt3 encoding and transmission. the circuit starts with a parallel-to-serial conversion, which converts the mii data from the mac into a 125 mhz serial bit stream. the data and control stream is th en converted into 4b/5b coding followed by a scrambler. the serialized data is further co nverted from nrz-to-nrzi format, and then transmitted in mlt3 current output. the output current is set by an external 1% 12.4 k ? resistor for the 1:1 transformer ratio. it has a typical rise/fall time of 4 ns and complies with the ansi tp-pmd standard regarding amplitude balance, overshoot, and timing jitter. the wave-s haped 10base-t out put is also incorporated in to the 100base-tx transmitter. 3.1.2 100base-tx receive the 100base-tx receiver function performs adaptive equalization, dc restoration, mlt3-to-nrz i conversion, data and clock recovery, nrzi-to-nrz co nversion, descrambling, 4b/5b decoding, and serial-to-parallel conversion. the receiv- ing side starts with the equalization filter to compensate for inter-symbol interference (isi) over the twisted pair cable. since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its char- acteristics to optimize the performance. in this design, th e variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then t unes itself for optimization. this is an ongoing process and can self-adjust against environmental changes such as temperature variations. the equalized signal then goes through a dc restoration and data conversion blo ck. the dc restoration circuit is used to compensate for the effect of base line wander and improve the dynamic range. t he differential data conversion circuit converts the mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock recovery circuit extracts the 125 mhz clock from the edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into the nrz format. the signal is then sent through the descrambler followed by the 4b/5b decoder. finally, the nrz serial data is converted to the mii format and provided as the input data to the mac. 3.1.3 pll clock synthesizer the KSZ8795clx generates 125 mhz, 83 mh z, 41 mhz, 25 mhz, and 10 mhz clocks for system timing. internal clocks are generated from an external 25 mhz crystal or oscillator. 3.1.4 scrambler/de-scrambler (100base-tx only) the purpose of the scrambler is to spread the power spectrum of the signal in order to reduce emi and baseline wander. the data is scrambled through the use of an 11-bit wide linear feedback shift register (lfsr). this can generate a 2047- bit non-repetitive sequence. the receiver will then descrambl e the incoming data stream with the same sequence at the transmitter. downloaded from: http:///
KSZ8795clx ds00002112a-page 14 ? 2016 microchip technology inc. 3.1.5 10base-t transmit the 10base-t output driver is incorporat ed into the 100base-t driver to allow transmission with the same magnetics. they are internally wave-shaped and pr e-emphasized into outputs with a typical 2. 3v amplitude. the harmonic contents are at least 27 db below the fundamental when dr iven by an all-ones manchester-encoded signal. 3.1.6 10base-t receive on the receive side, input buffers and level detecting squelch circuits are employed. a differential input receiver circuit and a pll perform the decoding function. the manchester-enc oded data stream is separated into a clock signal and nrz data. a squelch circuit rejects signal s with levels less than 400 mv or with short pulse widths in order to prevent noises at the rxp or rxm input from falsely triggering the decoder. when the input exceeds the squelch limit, the pll locks onto the incomi ng signal and the ksz 8795clx decodes a data frame. the re ceiver clock is maintained active during idle periods in between data reception. 3.1.7 mdi/mdi-x auto crossover to eliminate the need for crossover cables between simila r devices, the KSZ8795clx supports hp auto-mdi/mdi-x and ieee 802.3u standa rd mdi/mdi-x auto crossover. note t hat hp auto-mdi/mdi-x is the default. the auto-sense function detects remote transmit and receive pa irs and correctly assigns tran smit and receive pairs for the KSZ8795clx device. this feature is extremely useful when end users are unaware of cable types, and also, saves on an additional uplink configuration connection. the auto-cro ssover feature can be disabled through the port control registers, or miim phy registers. the ieee 802.3u standard mdi and mdi-x definitions are illustrated in ta b l e 3 - 1 . 3.1.7.1 straight cable a straight cable connects an mdi device to an mdi-x device, or an mdi-x device to an mdi device. figure 3-1 depicts a typical straight cable connection between a nic card (mdi) and a switch, or hub (mdi-x). table 3-1: mdi/mdi-x pin definitions mdi mdi-x rj-45 pins signals rj-45 pins signals 1 td+ 1 rd+ 2t d C2r d C 3 rd+ 3 td+ 6 rdC 6 tdC figure 3-1: typical straight cable connection downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 15 KSZ8795clx 3.1.7.2 crossover cable a crossover cable connects an mdi device to another mdi device, or an mdi-x device to another mdi-x device. the following diagram shows a typical crossover cable connectio n between two switches or hubs (two mdi-x devices). 3.1.8 auto-negotiation the KSZ8795clx conforms to the auto-negotiation prot ocol as described by the 802.3 committee. auto-negotiation allows unshielded twisted pair (utp) link partners to select the highest common mode-of-oper ation. link partners adver- tise their capabilities to each other and then compare their ow n capabilities with those they received from their link part- ners. the highest speed and duplex setting that is common to the two link partners is selected as the mode-of-operation. auto-negotiation is supported for the copper ports only. the following list shows the speed and duplex operation mode (highest to lowest): 100base-tx, full-duplex 100base-tx, half-duplex 10base-t, full-duplex 10base-t, half-duplex if auto-negotiation is not su pported or the KSZ8795clx link partner is forced to bypass auto-negotiation, the KSZ8795- clx sets its operating mode by observing the signal at its receiver. this is known as parallel detection, and allows the KSZ8795clx to establish link by listening for a fixed-signal protocol in the absence of auto-negotiation advertisement protocol. the auto-negotiation link up process is shown in figure 3-3 . figure 3-2: typical crossover cable connection receive pair receive pair transmit pair 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 transmit pair crossover cable 10/100 ethernet media dependent interface 10/100 ethernet media dependent interface modular connector (rj-45) hub (repeater or switch) modular connector (rj-45) hub (repeater or switch) downloaded from: http:///
KSZ8795clx ds00002112a-page 16 ? 2016 microchip technology inc. 3.1.9 linkmd ? cable diagnostics the linkmd feature utilizes time-domain reflectometry (tdr) to analyze the cabling plant for common cabling problems such as open circuits, short circuits, and impedance mismatches. linkmd works by sending a pulse of known amplitude and duration down the mdi and mdi-x pairs and then analyzes the shape of the reflected signal. timing the pulse duration gives an indication of the distance to the cabling fault with maximum distance of 200m and accuracy of 2m. internal ci rcuitry displays the tdr information in a user-readable dig- ital format. note: cable diagnostics are only valid for copper connections only. 3.1.9.1 access linkmd is initiated by accessing the phy special control/st atus registers 26, 42, 58, 74 and the linkmd result registers 27, 43, 59, and 75 for ports 1, 2, 3, and 4 respectively; and in conjunction with the port control 10 register for ports 1, 2, 3, and 4 respectively to disable auto-mdi/mdi-x. alternatively, the miim phy registers 0 and 1d can also be used for linkmd access. 3.1.9.2 usage the following is a sample procedure for using link md with registers {26, 27, and 29} on port 1: 1. disable auto mdi/mdi-x by writing a 1 to register 29, bit[2] to enable manual control over the differential pair used to transmit the linkmd pulse. 2. start cable diagnostic test by writing a 1 to r egister 26, bit[4]. this enable bit is self-clearing. 3. wait (poll) for register 26, bit[4] to return a 0, and indicating cable diagnostic test is completed. 4. read cable diagnostic test results in register 26, bits [6:5]. the results are as follows: figure 3-3: auto-negotiatio n and parallel operation downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 17 KSZ8795clx 00 = normal condition (valid test) 01 = open condition detected in cable (valid test) 10 = short condition detected in cable (valid test) 11 = cable diagnostic test failed (invalid test) the 11 case, invalid test, occurs when the KSZ8795clx is u nable to shut down the link partner. in this instance, the test is not run, since it would be impossible for the KSZ8795clx to determine if the detected signal is a reflection of the signal generated or a signal from another source. 5. get distance to fault by concatenating register 26, bit[0] and register 27, bits [7:0]; and multiplying the result by a constant of 0.4. the distance to the cable fault can be determined by the following formula: d (distance to cable fault, expressed in mete rs) = 0.4 x (register 26, bit[0], register 27, bits [7:0]) concatenated value of registers 26 bit[0] and 27 bits [7:0] should be converted to decimal before multiplying by 0.4. the constant (0.4) may be calibrated for different cabling co nditions, including cables with a velocity of propagation that varies significantly from the norm. for ports 2, 3, 4, and using the miim phy registers, linkmd usage is similar. 3.1.9.3 a linkmd example the following is a sample procedure for using li nkmd on ports 1, 2, 3, and 4 with force mdi-x mode: //disable mdi/mdi-x and force to mdi-x mode //w is write the register. r is read register below w 1d 04 w 2d 04 w 3d 04 w 4d 04 //set internal registers temporary by indirect registers, adjust for linkmd w 6e a0 w 6f 4d w a0 80 //enable linkmd testing with fault cable for ports 1, 2, 3 and 4 w 1a 10 w 2a 10 w 3a 10 w 4a 10 //wait until port register control 8 bit[4] returns a 0 (self clear) //diagnosis results r 1a r 1b r 2a r 2b r 3a r 3b r 4a r 4b //for example on port 1, the result analysis bas ed on the values of the register 0x1a and 0x1b //the register 0x1a bits[6-5] are for the open or the short detection. //the register 0x1a bit[0] + the register 0x1b bits [7-0] = cdt_fault_count [8-0] //the distance to fault is about 0.4 x (cdt_fault_count [8-0]) downloaded from: http:///
KSZ8795clx ds00002112a-page 18 ? 2016 microchip technology inc. 3.1.10 on-chip termination and internal biasing the KSZ8795clx reduces the board cost and simplifies the bo ard layout by using on-chip termination resistors for all ports and rx/tx differential pairs without the external termination resistors. the combination of the on-chip termination and the internal biasing will save more pcb spacing and po wer consumption, compared using external biasing and ter- mination resistors for multiple switches , because the transformers dont consum e the power anymore. the center taps of the transformer shouldnt need to be tied to the analog power. 3.2 media access controller (mac) operation the KSZ8795clx strictly abi des by ieee 802.3 standards to maximize compatibility. 3.2.1 inter-pac ket gap (ipg) if a frame is successfully transmitted, the 96-bit time ipg is measured between the two consecutive mtxen. if the cur- rent packet is experiencing collision, the 96-bit ti me ipg is measured from mcrs and the next mtxen. 3.2.2 backoff algorithm the KSZ8795clx implements the ieee standard 802.3 binary exponential backoff algorithm, and optional aggressive mode backoff. after 16 collisions, the packet will be optionally dropped, depending on the chip configuration in register 3. 3.2.3 late collision if a transmit packet experiences collisions after 512- bit times of the transmission, the packet will be dropped. 3.2.4 illegal frames the KSZ8795clx discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes in register 4. for special applications, the KSZ8795clx can also be programmed to accept frames up to 2k bytes in reg- ister 3 bit[6]. since the KSZ8795clx supports vlan tags, t he maximum sizing is adjusted when these tags are present. 3.2.5 flow control the KSZ8795clx supports standard 802.3x flow control frames on both transmit and receive sides. on the receive side, if the KSZ8795clx receives a pause control frame, the KSZ8795clx will not transmit the next normal frame until the timer, specified in the pause control frame, expires. if an other pause frame is received before the current timer expires, the timer will be updated with the new value in the second pause fr ame. during this period (being flow controlled), only flow-control packet s from the KSZ8795clx will be transmitted. on the transmit side, the KSZ8795clx has intelligent and efficient ways to determine when to invoke flow control. the flow control is based on availability of the system reso urces, including avail able buffers, availabl e transmit queues and available receive queues. the KSZ8795clx flow controls a port that has just received a packet if the destination port resource is busy. the KSZ8795clx issues a flow control frame (xoff), containing the maximum pause time defined in ieee standard 802.3x. once the resource is freed up, the KSZ8795clx sends out the other flow control frame (xon) with zero pause time to turn off the flow control (turn on transmission to the port). a hysteresis feature is also provided to prevent over- activation and deactivation of the flow control mechanism. the KSZ8795clx flow controls all ports if the receive queue becomes full. 3.2.6 half-duplex back pressure the KSZ8795clx also provides a half-duplex back pressure opti on (note that this is not in ieee 802.3 standards). the activation and deactivation conditions are the same as the ones given for full-duplex mode. if back pressure is required, the KSZ8795clx sends preambles to defer the other station's transmission (carrier sense deference). to avoid jabber and excessive deference as defined in ieee 802.3 standards , after a certain period of time, the KSZ8795clx discon- tinues carrier sense but raises it quickly after it drops packets to inhibit other tr ansmissions. this shor t silent time (no carrier sense) is to prevent other stat ions from sending out packets and keeps ot her stations in a carrier sense-deferred state. if the port has packets to send during a back pressure si tuation, the carrier sense-type back pressure is interrupted and those packets are transmitted instead. if there are no more packets to send, carri er sense-type back pressure becomes active again until switch resour ces are free. if a collision occurs, the binary exponential backoff algorithm is downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 19 KSZ8795clx skipped and carrier sense is generated immediately, reducing the chance of further colliding and maintaining carrier sense to prevent reception of packets. to ensure no packet loss in 10base-t or 100base-tx half-duplex modes, the user must enable the following: aggressive backoff (register 3, bit[0]) no excessive collision drop (register 4, bit[3]) back pressure (register 4, bit[5]) these bits are not set as the default because this is not the ieee standard. 3.2.7 broadcast storm protection the KSZ8795clx has an intelligent option to protect the switch system from receiving too many broadcast packets. broadcast packets are normally forwarded to all ports except the source port and thus us e too many switch resources (bandwidth and available space in transmit queues). the KSZ8795clx has the option to include multicast packets for storm control. the broadcast storm rate parameters are pr ogrammed globally and can be enabled or disabled on a per port basis. the rate is based on a 50 ms (0.05s) interval fo r 100bt and a 500 ms (0.5s) interval for 10bt. at the begin- ning of each interval, the counter is cleared to zero and t he rate limit mechanism starts to count the number of bytes during the interval. the rate definition is described in regi sters 6 and 7. the default setting for registers 6 and 7 is 0x4a (74 decimal). this is equal to a rate of 1%, calculated as follows: 148.80 frames/sec x 50 ms (0.05s)/interval x 1% = 74 frames/interval (approx.) = 0x4a 3.3 switch core 3.3.1 address look-up the internal look-up table stores mac addresses and their associated information. it contains a 1k unicast address table plus switching information. the KSZ8795clx is guaranteed to learn 1k addresses and distinguishes itself from a hash-based look-up table, which, depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn. 3.3.2 learning the internal look-up engine updates its table with a new entry if the following conditions are met: the received packets source address (sa) does not exist in the look-up table. the received packet is good; the packet has no receiving errors and is of legal length. the look-up engine inserts the qualified sa into the table, along with the port number and time stamp. if the table is full, the last entry of the table is deleted first to make room for the new entry. 3.3.3 migration the internal look-up engine also monitors whether a station is moved. if this occurs, it updates the table accordingly. migration happens when the following conditions are met: the received packets sa is in the table but t he associated source port information is different. the received packet is good; the packet has no receiving errors and is of legal length. the look-up engine will update the existing record in the table with the new source port information. 3.3.4 aging the look-up engine will update the time stamp information of a record whenever the corresponding sa appears. the time stamp is used in the aging process. if a record is not updated for a period of time, the look-up engine will remove the record from the table. the look-up engine constantly performs the aging pr ocess and will continuously remove aging records. the aging period is 300s (75s). this featur e can be enabled or disabled through register 3 bit[2]. 3.3.5 forwarding the KSZ8795clx will forward packets using an algorithm that is depicted in the following flowcharts. figure 3-4 shows stage one of the forwarding algorithm wh ere the search engine looks up the vlan id, static table, and dynamic table for the destination address, and comes up with port to forward 1 (ptf1). ptf1 is then further modified by the spanning tree, igmp snooping, port mirroring, and port vlan processe s and authentication to come up with port to forward 2 (ptf2), as shown in figure 3-4 . the authentication and acl have highest priori ty in the forwarding process; acl result will overwrite the result of the forwarding pr ocess. this is where the packet will be sent. downloaded from: http:///
KSZ8795clx ds00002112a-page 20 ? 2016 microchip technology inc. the KSZ8795clx will not forward the following packets: error packets. these include framing errors, frame c heck sequence (fcs) errors, alignment errors, and illegal size packet errors. ieee802.3x pause frames. KSZ8795clx intercepts these packe ts and performs full duplex flow control accord- ingly. "local" packets. based on destination address (da) lookup, if the destination port from the lookup table matches the port from which the packet originat ed, the packet is defined as "local." 3.3.6 switching engine the KSZ8795clx features a high-performance switching engine to move data to and from the macs packet buffers. it operates in store and forward mode, while the efficient switching mechanism reduces overall latency. the KSZ8795- clx has a 64 kb internal frame buffer. this resource is s hared between all five ports. there are a total of 512 buffers available. each buffer is sized at 128 bytes. 3.4 power and power management the KSZ8795clx device requires 3.3v analog power. an extern al 1.2v ldo provides the necessary 1.2v to power the analog and digital logic cores. the various i /os can be operated at 1.8v, 2.5v, and 3.3v. ta b l e 3 - 2 illustrates the various voltage options and requirements of the device. figure 3-4: destination address lookup and resolution flow chart table 3-2: KSZ8795clx voltage options and requirements power signal name device pin requirement vddat 2, 12, 76 3.3v or 2.5v input power to the analog blocks of transceiver in the device. vddio 34, 48, 70 choice of 1.8v or 2.5v or 3.3v for the i/o circuits. these input power pins power the i/o circuitry of the device. start no - search vlan table - ingress vlan filtering - discard npvid check - search based on da or da + fid - search based on da + fid yes found not found - check receiving port?s receive enable bit - check destination port?s transmit enable bit - check whether packets are special (bpdu) - applied to mac (#1 to #4) - mac #5 is reserved for c - igmp will be forwarded to port 5 - rx mirror - tx mirror - rx or tx mirror - rx and tx mirror ptf 1 spanning tree process igmp process port mirror process port vlan membership check ptf 2 vlan id valid? search static array search address look-up table ptf 2 get ptf 1 from address table get ptf 1 from vlan table get ptf 1 from static array ptf 1 = null not found found port authentication and acl downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 21 KSZ8795clx the KSZ8795clx supports enhanced powe r management in a low power state, wi th energy detection to ensure low power dissipation during device idle periods. there are mu ltiple operation modes under the power management function which are controlled by the register 14 bits[4 :3] and the port control 10 register bit[3] as: register 14 bits[4:3] = 00 normal operation mode register 14 bits[4:3] = 01 energy detect mode register 14 bits[4:3] = 10 soft power-down mode register 14 bits[4:3] = 11 reserved the port control 10 register 29, 45, 61, 77 bi t[3] = 1 are for the por t-based power-down mode. table 3-3 indicates all internal function blocks status under four different power management operation modes. 3.4.1 normal operation mode this is the default setting bits[4:3] = 00 in register 14 after chip power-up or hardware reset. when KSZ8795clx is in normal operation mode, all pll clocks are running, phy and mac are on, and the host interfac e is ready for cpu read or writes. during normal operation mode, the host cpu can set the bits [4:3] in register 14 to change the current normal operation mode to any one of the other three power management operation modes. 3.4.2 energy detect mode energy detect mode provides a mechanism to save more power than in the normal operation mode when the KSZ8795- clx port is not connected to an active link partner. in th is mode, the device will save more power when the cables are unplugged. if the cable is not plugged in, the device can au tomatically enter a low power state: the energy detect mode. in this mode, the device will keep transm itting 120 ns width pulses at a rate of 1 pulse per second. once activity resumes due to plugging a cable in or attempting by the far end to establish link, the device can automatically power up to normal power state in energy detect mode. energy detect mode consists of two states, normal power state and low-power state. while in low power state, the device reduces power consumption by disabling all circuitry except the energy-detect circ uitry of the receiver. the energy detect mode is entered by setting bits [4:3] = 01 in register 14. when the KSZ8795clx is in this mode, it will monitor the cable energy. if there is no energy on the cable for a time longer than the pre-configured value at bits [7:0] go-sleep time in register 15, KSZ8795clx will go into lo w power state. when KSZ8795clx is in low power state, it will keep monitoring the cable energy. once the energy is det ected from the cable, the device will enter normal power state. when the device is at normal power state, it is able to transmit or receive packet from the cable. 3.4.3 soft power-down mode the soft power-down mode is entered by setting bits [4:3] = 10 in register 14. when KSZ8795clx is in this mode, all pll clocks are disabled, also all of phys and the macs are off. any dumm y host access will wake -up this device from current soft power down mode to normal operation mode and in ternal reset will be issued to make all internal registers go to the default values. vdd12a 1 1.2v core power. filtered 1.2v input voltage. these pins feed 1.2v to power the internal analog and digital cores. vdd12d 26, 42, 73 gnda 3, 21, 78 analog ground. gndd 27, 33, 47, 61, 71 digital ground. table 3-3: internal function block status KSZ8795clx function blocks power management operation modes normal mode energy detect mode soft power-down mode internal pll clock enabled disabled disabled tx/rx phy enabled energy detect at rx disabled mac enabled disabled disabled host interface enabled disabled disabled table 3-2: KSZ8795clx voltage options and requirements (continued) power signal name device pin requirement downloaded from: http:///
KSZ8795clx ds00002112a-page 22 ? 2016 microchip technology inc. 3.4.4 port-based power-down mode in addition, the KSZ8795clx features a per-port power down mode. to save power, a phy port that is not in use can be powered down via the port control 10 regist er bit[3], or miim phy register 0 bit[11]. 3.4.5 energy effici ent ethernet (eee) along with supporting different types of power saving m odes (h/w power down, s/w power down, and energy detect mode), the KSZ8795clx extends the green function capability by supporting energy efficient ethernet (eee) features defined in ieee p802.3az, march 2010. both 10base-t and 100base-tx eee functions are supported in KSZ8795- clx. in 100base-tx the eee operation is asymmetric on th e same link, which means o ne direction could be at low- power idle (lpi) state, in the meanwhile, another direction c ould exist packet transfer activity. different from other type of power saving mode, eee is able to ma intain the link while power saving is ac hieved. based on eee specification, the energy saving from eee is don e at phy level. KSZ8795clx reduces the po wer consumption not only at phy level but also at mac and switch level by shutti ng down the unused clocks as much as po ssible when the devic e is at low-power idle phase. the KSZ8795clx supports the 802.3az ieee standard for both 10 mbps and 100 mbps interfaces. the eee capability combines switch, mac, and phy to support operation in the lpi mode. when the lpi mode is enabled, systems on both sides of the link can save power dur ing periods of low link utilization. eee implementation provides a protocol to coordinate transi tions to or from lower power consumption without changing the link status and without dropping or corrupting frames. the transition time into and out of the lower power consump- tion is kept small enough to be transparent to upper layer protocols and applications. eee specifies means to exchange capabilities between link partners to determine whether eee is supported and to select the best set of parameters com- mon to both sides. besides supporting the 100base-tx phy eee, KSZ8795clx al so supports 10base-t with reduced transmit ampli- tude requirements for 10 mbps mode to allow a reduction in power consumption. figure 3-5: ieee transmit and receive signaling paths idle quite transmit path switch issue or terminate lpi request map lpi request to lpi mii pattern pcs (phy layer) idle/data wakeup quiet/sleep quiet sleep/refresh quiet sleep idle data mac receive path control/status signals lpi status signals map lpi/p/ and quiet state to lpi mii pattern idle quite pcs (phy layer) idle/data wakeup quiet/sleep quiet sleep/refresh quiet sleep idle data mac clock control status register test control downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 23 KSZ8795clx 3.4.5.1 lpi signaling lpi signaling allows switch to indicate to the phy, and to th e link partner, that a break in the data stream is expected, and switch can use this information to enter power-saving mo des that require additional time to resume normal opera- tion. lpi signaling also informs the switch when the link partner has sent such an indication. the definition of lpi sig- naling uses of the mac for simplified full duplex operatio n (with carrier sense deferral). this provides full duplex operation but uses the carrier sense signal to defer transmission when the phy is in the lpi mode. the decision on when to signal lpi (lpi request) to the link pa rtner is made by the switch and communicated to the phy through mac mii interface. the switch is also informed when the link partner is signaling lpi, indication of lpi activation (lpi indication) on the mac interface. the conditions under which switch decid es to send lpi, and what actions are taken by switch when it receives lpi from the link partner, are specified in implementation section. 3.4.5.2 lpi assertion without lpi assertion, the normal traffic transition continues on the mii interface. as soon as an lpi request is asserted, the lpi assert function starts to transmit the assert lpi encoding on the mii and stop the mac from transmitting normal traffic. once the lpi request is de-asse rted, the lpi assert function starts to transmit the normal inter-frame encoding on the mii again. after a delay, the mac is allowed to start tr ansmitting again. this delay is provided to allow the link partner to prepare for normal operation. figure 3-6 illustrates the eee lpi betw een two active data idles. 3.4.5.3 lpi detection in the absence of assert lpi encoding on the receive mii, the lpi detect function maps the receive mii signals as nor- mal conditions. at the start of lpi, indi cated by the transition from normal inter-f rame encoding to the assert lpi encod- ing on the receive mii, the lpi detect function continues to indicate idle on interface, and asserts lp_idle indication. at the end of lpi, indicated by the transition from the a ssert lpi encoding to any ot her encoding on the receive mii, lp_idle indication is de-asserted and the normal decoding operation resumes. 3.4.5.4 phy lpi transmit operation when the phy detects the start of assert lpi encoding on the mii, the phy signals sleep to its link partner to indicate that the local transmitter is entering lpi mode. the eee capability require s the phy transmitter to go quiet after sleep is signaled. lpi requests are passed from one end of the link to the other and system energy savings can be achieved even if the phy link does not go into a low power mode. the transmit function of the local phy is periodically enabled in order to transmit refres h signals that are used by the link partner to update adaptive filters and timing circuits. this maintains link integrity. this quiet-refresh cycle continues until the reception of the normal inter-frame encoding on t he mii. the transmit function in the phy communicates this to the link partner by sending a wake signal for a predefin ed period of time. the phy then enters the normal operating state. no data frames are lost or corrupted du ring the transition to or from the lpi mode. in 100bt/full-duplex eee operation, refresh transmission are used to maintain link and the quiet periods are used for the power saving. approximately, every 20 ms to 22 ms a refr esh of 200 s to 220 s is sent to the link partner. the refresh transmission and quiet periods are shown in figure 3-6 . downloaded from: http:///
KSZ8795clx ds00002112a-page 24 ? 2016 microchip technology inc. 3.4.5.5 phy lpi receive operation on receive, entering the lpi mo de is triggered by the reception of a sleep signal from the link partner, which indicates that the link partner is about to enter the lpi mode. after sending the sleep signal, the link partner ceases transmission. when the receiver detects the sleep signal, the local phy i ndicates assert lpi on the mii and the local receiver can disable some functionality to reduce powe r consumption. the link part ner periodically transmits refresh signals that are used by the local phy. this quiet-refresh cycle continues un til the link partner initiates transition back to normal mode by transmitting the wake signal for a predetermined period of time controlled by the lpi assert function. this allows the local receiver to prepare for normal operation and transitio n from the assert lpi encoding to the normal inter-frame encoding on the mii. after a system specified recovery ti me, the link supports the nominal operational data rate. 3.4.5.6 negotiation with eee capability the eee capability shall be advertised during the auto-negot iation stage. auto-negotiation provides a linked device with the capability to detect the abilitie s supported by the device at the other end of the link, determine common abilities, and configure for joint operation. auto-negotiation is pe rformed at power up or reset, on command from management, due to link failure, or due to user intervention. during auto-negotiation, both link partners indicate their eee capabilities . eee is supported only if during auto-nego- tiation both the local device and link partner advertise the eee capability for the resolved phy type. if eee is not sup- ported, all eee functionality is disabled and the lpi client does not assert lpi. if eee is supported by both link partners for the negotiated phy type, then the eee function can be used independently in either direction. 3.4.6 wake-on-lan (wol) wake-on-lan (wol) allows a computer to be turned on or woken up by a network message. the message is usually sent by a program executed on another computer on the same local area net work. wake-up frame events are used to wake the system whenever mean ingful data is presented to the system over the network. examples of meaningful data include the reception of a magic packet?, a management request from a remote administrator, or simply network traffic directly targeted to the lo cal system. the KSZ8795cl x can be programmed to notify the host of the wake-up frame detection with the assertion of the inte rrupt signal (intr_n) or assertion of the power management event signal (pme). the pme control is by pme indirect registers. KSZ8795clx mac supports the detection of the following wake-up events: detection of energy signal over a pre- configured value: port pme control st atus register bit[0 ] in pme indirect registers. detection of a link-up in the network link state: port pm e control status register bit[1] in the pme indirect regis- ters. receipt of a magic packet: port pme control status register bit[2] in th e pme indirect registers. figure 3-6: traffic activi ty and eee lpi operations active low power active tw_phy tw_system quiet quiet quiet ts tq tr data/ idle data/ idleidle wake refreshrefresh sleep ts = the period of time that the phy transmits the sleep signal before turning all transmitters off, 200 ts 220 used in 100 base-tx. tq = the period of time that the phy remains quiet before sending the refresh signal, 20_000 tq 22_000 used in 100base-tx. tr = duration of the refresh signal, 200 tr 220 used in 100base-tx. downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 25 KSZ8795clx there are also other types of wake-up ev ents that are not listed here as manu facturers may choose to implement these in their own ways. 3.4.6.1 direction of energy the energy is detected from the cable and is continuously presented for a time longer than pre-configured value, espe- cially when this energy change may impact the level at which the system should re-enter to the normal power state. 3.4.6.2 direction of link-up link status wake events are useful to indicate a linkup in the networks connectivity status. 3.4.6.3 magic packet the magic packet is a broadcast frame containing anywhere within its payload 6 bytes of all 1s (ff ff ff ff ff ff) followed by sixteen repetitions of the target computer's 48-b it da mac address. since the magic packet is only scanned for the above string, and not actually pars ed by a full protocol stack, it may be sent as any network- and transport-layer protocol. magic packet technology is used to remotely wake up a sleeping or powered off pc on a lan. this is accomplished by sending a specific packet of information, called a magic packe t frame, to a node on the network. when a pc capable of receiving the specific fram e goes to sleep, it enables the magic packet rx mode in the lan controller, and when the lan controller receives a magic packet frame, it will aler t the system to wake up. on ce the KSZ8795clx has been enabled for magic packet detection in port pme control mask register bit[2] in the pme indirect register, it scans all incoming frames addressed to the node for a specific data seq uence, which indicates to the controller this is a magic packet frame. a magic packet frame must also meet th e basic requirements for the lan technology chosen, such as source address (sa), destination address (da), which may be the receiving stations ieee mac address, or a multicast or broadcast address and crc. the specific sequence consists of 16 dupl ications of the mac address of this node, with no breaks or interruptions. this sequence can be located anywhere within the packet, but must be preceded by a synchronization stream. the synchronization stream is defined as 6 bytes of 0xff. the device will also accept a broadcast frame, as long as the 16 duplications of the ieee address match the address of the machine to be awakened. example of magic packet: if the ieee address for a particular node on a network is 11 h 22h, 33h, 44h, 55h, 66h, the lan controller would be scan- ning for the data sequence (assuming an ethernet frame): da - sa - type - ff ff ff ff ff ff - 11 22 33 44 55 66 -11 22 33 44 55 66-11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 -1 1 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 3344 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 -misc-crc. there are no further restrictions on a magic packet frame. for instance, the sequence could be in a tcp/ip packet or an ipx packet. the frame may be bridged or routed across t he network without affecting its ability to wake-up a node at the frames destination. if the scans do not find the specific sequence shown above, it discards the frame and takes no further action. if the KSZ8795clx detects the data sequenc e, however, it then alerts the pcs power management circuitry (assert the pme pin) to wake-up the system. 3.4.7 interrupt (int_n/pme_n) int_n is an interrupt signal that is used to inform the exte rnal controller that there has been a status update in the KSZ8795clx interrupt status register. bits [3:0] of register 125 are the interrupt mask control bits to enable and disable the conditions for asserting the int_n signal. bits [3:0] of r egister 124 are the interrupt status bits to indicate which interrupt conditions have occurred. the interrupt status bits are cleared after reading those bits in the register 124. pme_n is an optional pme interrupt signal that is used to inform the external controller that there has been a status update in the KSZ8795clx interrupt status register. bits [4] of register 125 are the pme mask control bits to enable and disable the conditions for asserting the pme_n signal. bits [4] of register 124 are the pme interrupt status bits to indicate which pme interrupt conditions have occurred. the pme interrupt status bit[4] is cleared after reading this bit of the register 124. additionally, the interrupt pins of in t_n and pme_n eliminate the need for the processor to poll the switch for status change. downloaded from: http:///
KSZ8795clx ds00002112a-page 26 ? 2016 microchip technology inc. 3.5 interfaces the KSZ8795clx device incorporates a number of interfaces to enable it to be designed into a standard network envi- ronment as well as a vendor unique environmen t. the available interfaces are summarized in ta b l e 3 - 4 . the detail of each usage in this table is prov ided in the sections that follow. 3.5.1 configuration interface 3.5.1.1 spi slave serial bus configuration the KSZ8795clx can also act as an spi slave device. through the spi, the entire feature set can be enabled, including vlan, igmp snooping, mib counters, etc. the external spi master device can access any registers randomly in the data sheet shown. the spi mode can configure all the desired settings including indirect registers and tables. KSZ8795 default is in the start switch mode with the register 1 bit [0] =1, to disable the switch, write a "0" to register 1 bit [0]. two standard spi commands are supported (00000011 for r ead data, and 00000010 for write data). to speed configuration time, the KSZ8795clx also su pports multiple reads or writes. after a byte is written to or read from the KSZ8795clx, the internal address counter automatically increm ents if the spi slave select signal (spis_n) continues to be driven low. if spis_n is kept low after the first byte is read, the next byte at the next address will be shifted out on spiq. if spis_n is kept low after the first byte is written, bi ts on the master out slave input (spid) line will be written to the next address. asserting spis_n high terminates a read or write operation. this means that the spis_n signal must be asserted high and then low again before issuing another command and address. the address counter wraps back to zero once it reaches the highest addr ess. therefore the entire register set ca n be written to or read from by issuing a single command and address. the KSZ8795clx is able to support spi bus up to a maximu m of 50 mhz. a high-performance spi master is recom- mended to prevent internal counter overflow. to use the KSZ8795clx spi: 1. at the board level, connect the KSZ8795clx pins as detailed in table 3-5 . 2. configure the serial communication to spi slave mode by pulling down pin spiq with a pull-down resistor. 3. write configuration data to registers using a typical spi write data cycle as shown in figure 3-7 or spi multiple write as shown in figure 3-8 . note that data input on sda is regi stered on the rising edge of scl clock. 4. registers can be read and the configuration can be verified with a typical spi read data cycle as shown in figure 3-7 or a multiple read as shown in figure 3-8 . note that read data is regist ered out of spiq on the falling edge of scl clock. table 3-4: available interfaces interface type usage registers accessed spi configuration and register access [as slave serial bus] - external cpu or controller can r/w all internal registers thru this interface. all miim configuration and register access mdc/mdio capable cpu or cont rollers can r/w 4 phys reg- isters. phys only gmii data flow interface to the port 5 gmac using the standard gmii timing. n/a mii data flow interface to the port 5 gmac using the standard mii timing. n/a rgmii data flow interface to the port 5 gmac using the faster reduced gmii timing. n/a rmii data flow interface to the port 5 gmac using the faster reduced mii timing. n/a table 3-5: spi connections KSZ8795clx signal name micr oprocessor signal description spis_n (s_cs) spi slave select scl (s_clk) spi clock sda (s_di) master output. slave input. spiq (s_do) master input. slave output. downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 27 KSZ8795clx figure 3-7: spi access timing figure 3-8: spi mu ltiple access timing 0 1 0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 tr d7 d6 d5 d4 d3 d2 d1 d0 s_cs s_clk s_di s_do write command write address write data a) spi write cycle 0 1 1 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 tr d7 d6 d5 d4 d3 d2 d1 d0 s_cs s_clk s_di s_do read command read address read data b) spi read cycle s_cs s_clk s_di s_do s_cs s_clk s_di s_do write command write address write data a) spi write cycle read command read address read data b) spi read cycle 0 1 0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 tr d7 d6 d5 d4 d3 d2 d1 d0 s_cs s_clk s_di s_do write command write address write byte 1 a) spi multiple write cycle 0 1 1 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 tr d7 d6 d5 d4 d3 d2 d1 d0 s_cs s_clk s_di s_do read command read address read byte 1 b) spi multiple read cycle d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 s_cs s_clk s_di write byte 2 write byte n d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 s_cs s_clk s_do read byte 2 read byte n s_cs s_clk s_di s_do write command write address write byte 1 a) spi multiple write cycle read command read address read byte 1 b) spi multiple read cycle write byte 2 write byte n read byte 2 read byte n s_cs s_clk s_di s_do s_cs s_clk s_di s_cs s_clk s_do downloaded from: http:///
KSZ8795clx ds00002112a-page 28 ? 2016 microchip technology inc. 3.5.1.2 mii management interface (miim) the KSZ8795clx supports the standard ieee 802.3 mii managem ent interface, also known as the management data input/output (mdio) interface. this interface allows uppe r-layer devices to monitor and control the states of the KSZ8795clx. an external device with mdc/mdio capability is used to read the phy status or configure the phy set- tings. further details on the miim interfac e are found in the ieee 802.3u specification. the miim interface consists of the following: a physical connection that incorporates the data line mdio and the clock line mdc. a specific protocol that o perates across the aforementioned physical connection that allows an external controller to communicate with the KSZ8795clx device. access to a set of eight 16-bit registers, consisting of 8 standard miim registers [0:5h] , 1d and 1f miim registers per port. the miim interface mdc/mdio can operate up to a maximum clock speed of 25 mhz mdc clock. table 3-6 depicts the mii management interface frame format. note 3-1 preamble C consists of 32 1s start-of-frame C the start-of-frame is indicated by a 01 pattern. this pattern assures transitions from the default logic one line state to zero and back to one. read/write op code C the operation code for a read transa ction is 10, while the operation code for a write transaction is 01. phy address bits[4:0] C the phy address is five bits, allowing 32 unique phy addresses. the first phy address bit transmitted and received is the msb of the address. reg address bits[4:0] C the register address is five bits , allowing 32 individual registers to be addressed within each phy. the first register addr ess bit transmitted and received is the msb of the address. ta (turnaround) C the turnaround time is 2-bit time spacing between the register address field and the data field of a frame to avoid contention duri ng a read transaction. fo r a read transaction, both the master and the phys shall remain in a high- impedance state for the first bit time of the turnaround. the phy shall drive a zero bit during the second bit time of the turnaround of a read transaction. during a write transacti on, the master shall drive a one bi t for the first bit time of the turnaround and a zero bit for the second bit time of the turnaround. data bits[15:0] C the data field is 16 bits. the first data bit transmitted and received shall be bit[15] of the register being addressed. at the beginning of each transaction, the master device shall send a sequence of 32 contiguous logic 1 bits on mdio with 32 corresponding cycles on mdc as cl ock to provide device with a pattern that it can use to establish synchroniza- tion. device starts respond to any transaction only after observes a sequence of 32 contiguous one bits on mdio with 32 corresponding cycles on mdc. the miim interface does not have access to all the conf iguration registers in the KSZ8795clx. it can only access the standard miim register (see the miim registers section). the spi interface, on the other hand, can be used to access all registers with the entire KSZ8795clx feature set. 3.5.2 switch port 5 gmac interface the KSZ8795clx gmac5 interface suppor ts the gmii/mii/rgmii/rmii four interf aces protocols and shares one set of input/output signals. the purpose of th is interface is to provide a simple, in expensive, and easy-to implement intercon- nection between the gmac/mac sub layer and a gphy/phy . data on these interfaces are framed using the ieee ethernet standard. as such it consists of a preamble, st art of frame delimiter, ethernet headers, protocol-specific data and a cyclic redundancy check (crc) checksum. transmit and receive signals for gmii/m ii/rgmii/rmii interfaces shown in table 3-7 . table 3-6: mii management interface frame format ( note 3-1 ) preamble start of frame read/ write op code phy address bits[4:0] reg address bits[4:0] ta data bits[15:0] idle read 32 1s 01 10 aaaaa rrrrr z0 dddddddd_dddddddd z write 32 1s 01 01 aaaaa rrrrr 10 dddddddd_dddddddd z downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 29 KSZ8795clx 3.5.2.1 standard gm ii/mii interface for mii and gmii, the interface is capable of supporting 10 /100 mbps and 1000 mbps oper ation. data and delimiters are synchronous to clock references. it provides independ ent four-/eight-bit-wide transmit and receive data paths and uses signal levels, two media status si gnals are provided. the crs indicates th e presence of carrier, and the col indi- cates the occurrence of a collision. both half- and full-dupl ex operations are provided by mii and full-duplex operation is used for gmii. the gmii is based on the mii. mii signal names have been retained and the functions of most signals are the same, but additional valid combinations of signals have been defined for 1000 mbps operation. the gmii supports only 1000 mbps operation. operation at 10 mbps and 100 mbps is supported by the mii interface. the mii transfers data using 4-bit words (nibble) in each dire ction. it is clocked at 2.5/25 mhz to achieve 10/100 mbps speed. the gmii transfers data using 8-bit words (nibble) in each direction, clocked at 125 mhz to achieve 1000 mbps speed. 3.5.2.2 reduced gigabit media independent interface (rgmii) rgmii is intended to be an alternative to the ieee802.3u mii and the ieee802.3z gmii. the principle objective is to reduce the number of pins required to interconnect the gmac and the gphy in a cost effective and technology inde- pendent manner. in order to accomplish this objective, the data paths and all associated control signals will be reduced and control signals will be multiplexed together and both ed ges of the clock will be used. for gigabit operation, the clocks will operate at 125 mhz with the rising edge and fa lling edge to la tch the data. 3.5.2.3 reduced media independent interface (rmii) the reduced media independent interfac e (rmii) specifies a low pin count media independent interface (mii). the KSZ8795clx supports the rmii interface on the port 5 gmac5 and provides the following key characteristics: supports 10 mbps and 100 mbps data rates. uses a single 50 mhz clock reference (provided internally or externally): in internal mode, the chip provides a ref- erence clock from the rxc5 to the oppos ite clock input pin for rmii interface. in external mode, the chip receives 50 mhz reference clock from an external oscillator or opposite rmii interface. provides independent 2-bit wide (bi-bit) transmit and receive data paths. 3.5.2.4 port 5 gmac5 sw5-mii interface table 3-8 shows two connection methods. 1. the first is an external mac connecting in sw5-mii phy mode. 2. the second is an external phy connecting in sw5-mii mac mode. the mac mode or phy mode setting is det ermined by the strap pin 62 led2_1. table 3-7: signals of gmii/rgmii/mii/rmii direction type gmii rgmii mii rmii input (output) gtxc gtxc txc refclki input txer txer input txen txd_ctl txen txen input (output) col col input txd[7:0] txd[3:0 ] txd[3:0] txd[1:0] input (output) grxc grxc rxc rxc output rxer rxer rxer output rxdv rxd_ctl rxdv crs_dv input (output) crs crs output rxd[7:0] rxd[3: 0] rxd[3:0] rxd[1:0] downloaded from: http:///
KSZ8795clx ds00002112a-page 30 ? 2016 microchip technology inc. the mii interface operates in either mac mode or phy mode . these interfaces are nibble-wide data interfaces, so they run at one-quarter the network bit rate (not encoded). addition al signals on the transmit side indicate when data is valid or when an error occurs during transmission. likewise, the rece ive side has indicators that convey when the data is valid and without physical layer errors. for half-duplex operation, t here is a col signal that indicates a collision has occurred during transmission. note: normally mrxer would indicate a receive error coming from the physical layer device. mtxer would indicate a transmit error from the mac device. these signals are not appropriate for this configur ation. for phy mode operation with an external mac, if the device interfacing with t he KSZ8795clx has an mrxer pin, it can be tied low. for mac mode operation with an external phy, if the device interf acing with the KSZ8795clx has an mtxer pin, it can be tied low. 3.5.2.5 port 5 gmac5 sw5-gmii interface table 3-9 shows two gmii connection methods when connected to an external gmac or gphy. the first is an external gmac connecting in sw5-gmii gphy mode. the second is an external gphy connecting in sw5-gmii gmac mode. the gmac mode or gphy mode setting is det ermined by the strap pin 62 led2_1. table 3-8: port 5 sw5-mii connection mac-to-mac connection KSZ8795clx sw5-mii phy mode description mac-to-phy connection KSZ8795clx sw5-mii phy mode external mac KSZ8795clx sw5-mii signals type external phy KSZ8795clx sw5-mii signals type mtxen txen5 input transmit enable mtxen rxdv5 output mtxer txer5 input transmit error mtxer rxer5 output mtxd[3:0] txd5[3:0] input transmit data bit[3:0] mtxd[3:0] rxd5[3:0] output mtxc txc5 output transmit clock mtxc rxc5 input mcol col5 output collision detection mcol col5 input mcrs crs5 output carrier sense mcrs crs5 input mrxdv rxdv5 output receive data valid mrxdv txen5 input mrxer rxer5 output receive error mrxer txer5 input mrxd[3:0] rxd5[3:0] output receive data bit[3:0] mrxd[3:0] txd5[3:0] input mrxc rxc5 output receive clock mrxc txc5 input table 3-9: port 5 sw5-gmii connection gmac-to-gmac connection KSZ8795clx sw5-gmii gphy mode description gmac-to-gphy connection KSZ8795clx sw5-gmii gmac mode external gmac KSZ8795clx sw5-gmii signals type external gphy KSZ8795clx sw5-gmii signals type mrxdv txen5 input transmit enable mtxen rxdv5 output mrxer txer5 input transmit error mtxer rxer5 output mrxd[7:0] txd5[7:0] input transmit data bits[7:0] mtxd[7:0] rxd5[7:0] output mgrxc gtxc5 input transmit clock mgtxc grxc5 output downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 31 KSZ8795clx the port 5 gmac5 sw5-gmii interface operates at up to 1000 mbps. in 1gbps mode, gmii supports the full-duplex only. the gmii interface is 8-bits data in each direction. additional signals on the transmit side indicate when data is valid or when an error occurs during transmission. likewise, the receive side has indicators that convey when the data is valid and without physical layer errors. for half-duplex operation in 10/100 mbps mode, there is a col signal that indicates a collision has occurred during transmission. 3.5.2.6 port 5 gmac5 sw5-rgmii interface table 3-10 shows the rgmii reduced connections when c onnecting to an external gmac or gphy. the rgmii interface operates at up to a 1000 mbps speed rate. additional transmit and receive signals control the dif- ferent direction of the data transfer. this rgmii interf ace supports rgmii rev 2.0 with adjustable ingress clock and egress clock delay by the register 86 (0x56). for rgmii to correctly configure with the connection partner, register 86 (0x56) bits [4:3] need to be set up correctly. a configuration table is found in table 3-11 . mcol col5 output collision detection mcol col5 input mcrs crs5 output carrier sense mcrs crs5 input mrxen rxdv5 output receive data valid mrxdv txen5 input mtxer rxer5 output receive error mrxer txer5 input mrxd[7:0] rxd5[7:0] output receive data bits[7:0] mrxd[7:0] txd5[7:0] input mgtxc grxc5 output receive clock mgrxc gtxc5 input table 3-10: port 5 sw5-rgmii connection KSZ8795clx sw5-rgmii connection description external gmac/gphy KSZ8795clx sw5-rgmii signals type mrx_ctl txd5_ctl input transmit control mrxd[3:0] txd5[3:0] input transmit data bit[3:0] mrx_clk gtx5_clk input transmit clock mtx_clk rxd5_ctl output receive control mtxd[3:0] rxd5[3:0] output receive data bit[3:0] mgtx_clk grxc5 output receive clock table 3-11: port 5 sw5-rgmii clock de lay configuration with connection partner KSZ8795clx register 86 bits[4:3] configuration rgmii clock mode (receive and transmit) KSZ8795clx register 86 (0x56) KSZ8795clx rgmii clock delay/slew configuration connection partner rgmii clock configuration ( note 3-1 ) bit[4:3] = 11 mode ingress clock input bit[4] = 1 delay no delay egress clock output bit[3] = 1 delay no delay bit[4:3] = 10 mode ingress clock input bit[4] = 1 delay no delay egress clock output bit[3] = 1 no delay delay table 3-9: port 5 sw5-gmii connection (continued) gmac-to-gmac connection KSZ8795clx sw5-gmii gphy mode description gmac-to-gphy connection KSZ8795clx sw5-gmii gmac mode external gmac KSZ8795clx sw5-gmii signals type external gphy KSZ8795clx sw5-gmii signals type downloaded from: http:///
KSZ8795clx ds00002112a-page 32 ? 2016 microchip technology inc. note 3-1 processor with rgmii, an external gphy or KSZ8795clx back-to-back connection. for example, two KSZ8795 devices are the back-to-back connection. if one device set bit[4:3] =11, another one should set bit[4:3] = 00. if one device set bit[4:3] =01, another one should set bit[4:3] = 01 too. the rgmii mode is configured by th e strap-in pin led3 [1:0] =11 (default) or register 86 (0x5 6) bits[1:0] = 11 (default). the speed choice is by the strap-in pin led1_0 or register 86 (0x56) bit[6], the default speed is 1gbps with bit[6] = 1, set bit[6] = 0 is for 10/100 mbps speed in rgmii mode. KSZ8795clx provides register 86 bits[4:3] with the adjustable clock delay and register 164 bits[6:4] with the adjustable drive strength for best rgmii ti ming on board level in 1gbps mode. 3.5.2.7 port 5 gmac5 sw5-rmii interface the rmii specifies a low pin count mii. the KSZ8795clx supp orts rmii interface on port 5 and provides the following key characteristics: supports 10 mbps and 100 mbps data rates. uses a single 50 mhz clock reference (provided internally or externally): in internal mode, the chip provides a ref- erence clock from the rxc5 pin to the opposite clock input pin for rmii interface when port 5 rmii is set to clock mode. in external mode, the chip receives 50 mhz reference cl ock on the txc5/refclki5 pin from an external oscilla- tor or opposite rmii interface when the device is set to normal mode. provides independent 2-bit wide (bi-bit) transmit and receive data paths. for the details of sw5-rmii (port 5 gmac5 rmii) signal connection, see ta b l e 3 - 1 2 . when the device is strapped to normal mode, the reference clock comes from the txc5/refclki5 pin and will be used as the devices clock source. set the strap pin led1_1 can se lect the devices clock source either from the txc5/ref- clki5 pin or from an external 25 mhz crystal/oscillator clock on the xi/xo pin. in internal mode, when using an internal 50 mhz clock as sw5-rmii reference clock, the KSZ8795clx port 5 should be set to clock mode by the strap pin led2_1 or the port register 86 bit[7]. the clock mode of the KSZ8795clx device will provide the 50 mhz reference clock to the port 5 rmii interface. in external mode, when using an external 50 mhz clock sour ce as sw5-rmii reference clock, the KSZ8795clx port 5 should be set to normal mode by the strap pin led2_1 or th e port register 86 bit[7]. the normal mode of the KSZ8795- clx device will start to work when it receives the 50 mh z reference clock on the txc5/refclki5 pin from an external 50 mhz clock source. bit[4:3] = 01 mode ingress clock input bit[4] = 0 (default) no delay delay egress clock output bit[3] = 0 (default) delay no delay bit[4:3] = 00 mode ingress clock input bit[4] = 0 no delay delay egress clock output bit[3] = 0 no delay delay table 3-11: port 5 sw5-rgmii clock de lay configuration with connection partner (continued) KSZ8795clx register 86 bits[4:3] configuration rgmii clock mode (receive and transmit) KSZ8795clx register 86 (0x56) KSZ8795clx rgmii clock delay/slew configuration connection partner rgmii clock configuration ( note 3-1 ) downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 33 KSZ8795clx 3.6 advanced functionality 3.6.1 qos priority support the KSZ8795clx provides quality-of-service (qos) for applications such as voip and video conferencing. the KSZ8795clx offers one, two, or four priority queues per port by setting the port control 13 registers bit[1] and the port control 0 registers bit[0], the 1/2/4 queues split as follows: [port control 9 registers bit[1], control 0 bit[0]] = 00 single out put queue as default. [port control 9 registers bit[1], cont rol 0 bit[0]] = 01 egress port can be split into two priority transmit queues. [port control 9 registers bit[1], control 0 bit[0]] = 10 egress port can be split into four priority transmit queues. the four priority transmit queue is a new feature in the KSZ8795clx. queue 3 is the highest priority queue and queue 0 is the lowest priority queue. the port control 9 registers bit[1] and the port control 0 registers bit[0] are used to enable split transmit queues for ports 1, 2, 3, 4 and 5, respectively. if a port's transmit queue is not split, high priority and low priority packets have equal priority in the transmit queue. there is an additional option to either always deliver high priority packets first or to use programmable weighted fair queuing for the four priority queue scale by the port control 14, 15, 16 and 17 registers (default values are 8, 4, 2, 1 by their bits [6:0]). register 130 bit[7:6] prio_2q[1:0] is used when the 2-queue configuration is selected. these bits are used to map the 2-bit result of ieee 802.1p from the re gisters 128, 129 or tos/diffserv mapping from registers 144-159 (for 4 queues) into 2-queue mode with priority high or low. please see the descriptions of register 130 bits [7:6] for detail. 3.6.1.1 port-based priority with port-based priority, each ingress port is individually cl assified as a priority 0-3 receiving port. all packets received at the priority 3 receiving port are marked as high-priority and are sent to the high-priority transmit queue if the corre- sponding transmit queue is split. the port control 0 registers bits [4:3] is used to enable port-based priority for ports 1, 2, 3, 4 and 5, respectively. table 3-12: port 5 sw5-rmii connection sw5-rmii mac-to-mac connection (phy mode) description sw5-rmii mac-to-phy connection (mac mode) external mac KSZ8795clx sw5-rmii signals type external phy KSZ8795clx sw5-rmii signals type ref_clki rxc5 output 50 mhz in clock mode reference clock 50 mhz refclki5 input 50 mhz in normal mode crs_dv rxdv5/ crsdv5 output carrier sense/ receive data valid crs_dv txen5 input receive error rxer txer5 input rxd[1:0] rxd5[1:0] output receive data bit[1:0] rxd[1:0] txd5[1:0] input tx_en txen5 input transmit data enable tx_en rxdv5/ crsdv5 output txd[1:0] txd5[1:0] input transmit data bit[1:0] txd[1:0] rxd[1:0] output 50 mhz refclki5 input 50 mhz in normal mode reference clock ref_clki rxc5 output 50 mhz in clock mode downloaded from: http:///
KSZ8795clx ds00002112a-page 34 ? 2016 microchip technology inc. 3.6.1.2 802.1p-based priority for 802.1p-based priority, the KSZ8795clx examines the ingress (incoming) packets to determine whether they are tagged. if tagged, the 3-bit priority field in the vlan tag is retrieved and compared against the priority mapping value, as specified by the registers 128 and 129, both register 12 8 and 129 can map 3-bit priority field of 0-7 value to 2-bit result of 0-3 priority levels. the priority mapping value is programmable. figure 3-9 illustrates how the 802.1p priority field is embedded in the 802.1q vlan tag. the 802.1p-based priority is enabled by bi t[5] of the port control 0 registers fo r ports 1, 2, 3, 4 and 5, respectively. the KSZ8795clx provides the option to insert or remove th e priority tagged frame's header at each individual egress port. this header, consisting of the two-byte vlan protocol id (vpid) and the two-byte tag control information field (tci), is also referred to as the ieee 802.1q vlan tag. tag insertion is enabled by bit[2] of the port control 0 regist ers and the port control 8 registers to select which source port (ingress port) pvid can be inserted on the egress port for po rts 1, 2, 3, 4 and 5, respectively. at the egress port, untagged packets are tagged with the ingress ports default tag. the default tags are progra mmed in the port control 3 and control 4 registers for ports 1, 2, 3, 4 and 5, respectively. the KSZ8795clx will not add tags to already tagged packets. tag removal is enabled by bit[1] of the port control 0 regist ers for ports 1, 2, 3, 4 and 5, respectively. at the egress port, tagged packets will have their 802.1q vlan tags removed. the KSZ8795clx will not modify untagged packets. the crc is recalculated for both tag insertion and tag removal. 802.1p priority field re-mapping is a qos feature that allows the KSZ8795clx to set the user priority ceiling at any ingress port by the port control 2 register bit[7]. if the ingre ss packets priority field has a higher priority value than the default tags priority field of the ingress port, the packets prio rity field is replaced with the default tags priority field . 3.6.1.3 diffserv-based priority diffserv-based priority uses the tos registers (registers 14 4 to 159) in the advanced c ontrol registers sub-section. the tos priority control registers implement a fully decoded, 128-bit differentiated servic es code point (dscp) register to determine packet priority from the 6-bit tos field in the ip header. when the most significant six bits of the tos field are fully decoded, 64 code points for dscp result. these ar e compared with the corresponding bits in the dscp register to determine priority. 3.6.2 spanning tree support port 5 is the designated port for spanning tree support. the other ports (port 1 - port 4) can be configured in one of the five spanning tree states via the transmit enable, receive enable, and learning disable regist er settings in registers 18, 34, 50, and 66 for ports 1, 2, 3, and 4, respec- tively. the following description shows the port setting and software actions taken for each of the five spanning tree states. figure 3-9: 802.1p priority field format downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 35 KSZ8795clx the KSZ8795clx supports common spanning tree (cst). to suppo rt spanning tree, the host port (port 5) is the des- ignated port for the processor. the other ports can be confi gured in one of the five spanni ng tree states via transmit enable, receive enable and learning disable r egister settings in: port control 2 registers. ta b l e 3 - 1 3 shows the port setting and software actions taken for each of the five spanning tree states. table 3-13: port setting and software actions for spanning tree disable state port setting software action the port should not forward or receive any packets. learn- ing is disabled. "transmit enable = 0, receive enable = 0, learning disable = 1." the processor should not send any packets to the port. the switch may still send specific packets to the processor (packets that match some entries in the static table wit h overriding bit set) and the pro- cessor should discard those packets. note: processor is connected to port 5 via mii interface. address learning is disabled on the port in this state. blocking state port se tting software action only packets to the processor are for- warded. learning is disabled. "transmit enable = 0, receive enable = 0, learning disable = 1" the processor should not send any packe ts to the port(s) in this state. the processor should program the static mac table with the entries that it needs to receive (e.g., bpdu packets). the overriding bit should also be set so that the s witch will forward those specific pack- ets to the processor. address learning is disabled on the port in this state. listening state port setting software action only packets to and from the processor are forwarded. learning is disabled. "transmit enable = 0, receive enable = 0, learning disable = 1. the processor should program the static mac table with the entries that it needs to receive (e.g. bpdu packets). the overriding bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this state (see tail tagging mode section for details). address learning is disabled on the port in this state. learning state port setting software action only packets to and from the processor are forwarded. learning is enabled. transmit enable = 0, receive enable = 0, learning disable = 0. the processor should program the static mac table with the entries that it needs to receive (e.g., bpdu packets). the overriding bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this state (see tail tagging mode section for details). address learning is enabled on the port in this state. forwarding state port setting software action packets are for- warded and received normally. learning is enabled. transmit enable = 1, receive enable = 1, learning disable = 0. the processor should program the static mac table with the entries that it needs to receive (e.g., bpdu packets). the overriding bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this state (see tail tagging mode section for details). address learning is enabled on the port in this state. downloaded from: http:///
KSZ8795clx ds00002112a-page 36 ? 2016 microchip technology inc. 3.6.3 rapid spanning tree support there are three operational states of t he discarding, learning, and forwarding assigned to each port for rstp. discard- ing ports do not participate in the active topology and do not learn mac addresses. ports in the learning states learn mac addresses, but do not forward user traffic. ports in t he forwarding states fully participate in both data forwarding and mac learning. rstp uses only one type of bpdu calle d rstp bpdus. they are similar to stp configuration bpdus with the exception of a type field set to version 2 fo r rstp and version 0 for stp, and flag field carrying addi- tional information. 3.6.4 tail tagging mode the tail tag is only seen and used by the port 5 interface, which should be connected to a processor by the sw5-gmii, rgmii, mii, or rmii interfaces. one byte tail tagging is used to indicate the source/destination port on port 5. only bits [3:0] are used for the dest ination in the tail tagging byte. other bits are not used. the tail tag feature is enabled by settin g register 12 bit[1]. table 3-14: port setting and software actions for rapid spanning tree disable state port setting software action the state includes three states of the disable, blocking and listening of stp. "transmit enable = 0, receive enable = 0, learning disable = 1." the processor should not send any packets to the port. the switch may still send specific packets to the processor (packets that match some entries in the static table wit h overriding bit set) and the pro- cessor should discard those packets. when disable the ports learning capability (learning disable = 1), set the register 1 bit[5] and bit[4] will flush rapidly with the port-related entries in the dynamic mac table and static mac table. note: processor is connected to port 5 via mii interface. address learning is disabled on the port in this state. learning state port setting software action only packets to and from the processor are forwarded. learning is enabled. transmit enable = 0, receive enable = 0, learning disable = 0. the processor should program the static mac table with the entries that it needs to receive (e.g., bpdu packets). the overriding bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this state (see tail tagging mode section for details). address learning is enabled on the port in this state. forwarding state port setting software action packets are for- warded and received normally. learning is enabled. transmit enable = 1, receive enable = 1, learning disable = 0. the processor should program the static mac table with the entries that it needs to receive (e.g., bpdu packets). the overriding bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this state (see tail tagging mode section for details). address learning is enabled on the port in this state. figure 3-10: tail tag frame format downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 37 KSZ8795clx 3.6.5 igmp support there are two components involved with the support of the in ternet group management protoc ol (igmp) in layer 2. the first part is igmp snooping, the second part is this igmp packet which is sent back to the subscribed port. those com- ponents are as follows. 3.6.5.1 igmp snooping the KSZ8795clx traps igmp packets and forwards them only to the processor (port 5 sw5-rgmii/mii/rmii). the igmp packets are identified as ip packets (either ethernet ip packets, or ieee 802.3 snap ip packets) with ip version = 0x4 and protocol version number = 0x2. set re gister 5 bit[6] to 1 to enable igmp snooping. 3.6.5.2 igmp send back to the subscribed port once the host responds to the received igmp packet, the host should know the original igmp ingress port and send back the igmp packet to this port only, to avoid this igmp packet being broadcast to all ports which will downgrade the performance. with the tail tag mode enabled, the host will know the port which igmp packet has been received from tail tag bits [1:0] and can send back the response igmp packet to this subscribed port by setting bits [3:0] in the tail tag. enable tail tag mode by setting register 12 bit[1]. 3.6.6 ipv6 mld snooping the KSZ8795clx traps ipv6 multicast listener discovery (mld) packets and forwards them only to the processor (port 5). mld snooping is controlled by register 164 bit[2] (mld snooping enable) and register 164 bit[3] (mld option). with mld snooping enabled, the KSZ8795clx traps packets that meet all of the following conditions: ipv6 multicast packets hop count limit = 1 ipv6 next header = 1 or 58 (or = 0 with hop-by-hop next header = 1 or 58) if the mld option bit is set to 1, the KSZ8795clx traps packets with the following additional condition: - ipv6 next header = 43, 44, 50, 51, or 60 (or = 0 wi th hop-by-hop next header = 43, 44, 50, 51, or 60) table 3-15: tail tag rules ingress to port 5 (h ost to KSZ8795clx) bits[3:0] destination 0,0,0,0 reserved 0,0,0,1 port 1 (direct forward to port 1) 0,0,1,0 port 2 (direct forward to port 2) 0,1,0,0 port 3 (direct forward to port 3) 1,0,0,0 port 4 (direct forward to port 4) 1,1,1,1 port 1, 2, 3, and 4 (direct forward to port 1, 2, 3, 4) bits[7:4] 0,0,0,0 queue 0 is used at destination port 0,0,0,1 queue 1 is used at destination port 0,0,1,0 queue 2 is used at destination port 0,0,1,1 queue 3 is used at destination port 0,1,x,x anyhow send packets to specified port in bits[3:0] 1,x,x,x bits[6:0] will be ignor ed as normal (address look-up) egress from port 5 (KSZ8795clx to host) bits[1:0] source 0,0 port 1 (packets from port 1) 0,1 port 2 (packets from port 2) 1,0 port 3 (packets from port 3) 1,1 port 4 (packets from port 4) downloaded from: http:///
KSZ8795clx ds00002112a-page 38 ? 2016 microchip technology inc. for mld snooping, tail tag mode also needs to be enabled, so that the processor knows which port the mld packet was received on. this is achieved by setting register 12 bit[1]. 3.6.7 port mirroring support the KSZ8795clx supports port mirror as described in the following: 3.6.7.1 receive only mirror on a port all the packets received on the port will be mirrored on the sniffer port. for example, port 1 is programmed to be rx sniff, and port 5 is programmed to be the sniffer port. a packet, received on port 1, is destined to port 4 after the internal look-up. the KSZ8795clx will forward the packet to both port 4 and port 5. ks z8795clx can optionally for- ward even bad receiv ed packets to port 5. 3.6.7.2 transmit only mirror on a port all the packets transmitted on the port will be mirrored on the sniffer port. for example, port 1 is programmed to be tx sniff, and port 5 is programmed to be the sniffer port. a packe t, received on any of the ports, is destined to port 1 after the internal look-up. the KSZ8795clx will forward the packet to both ports 1 and 5. 3.6.7.3 receive and transmit mirror on two ports all the packets received on port a and transmitted on port b will be mirrored on the sniffer port. to turn on the and feature, set register 5 bit[0] to bit[1 ]. for example, port 1 is programmed to be rx sniff, port 2 is programmed to be tx sniff, and port 5 is programmed to be the sniffer port. a packet, received on port 1, is destined to port 4 after the internal look-up. the KSZ8795clx will forward the packet to po rt 4 only because it does not meet the and condition. a packet, received on port 1, is destined to port 2 afte r the internal look-up. the KSZ8795clx will forward the packet to both port 2 and port 5. multiple ports can be selected to be rx sniffed or tx sniffed. any port can be selected to be the sniffer port. all these per port features can be selected through the port control 1 register. 3.6.8 vlan support the KSZ8795clx supports 128 active vlans and 4096 po ssible vids specified in ieee 802.1q. the KSZ8795clx provides a 128-entry vlan table, which co rrespond to 4096 possible vids and converts to fid (7 bits) for address look- up max 128 active vlans. if a non-tagged or null-vid-tagged packet is received, then the ingress port vid is used for look-up when 802.1q is enabled by the global register 5 cont rol 3 bit[7]. in the vlan mode, the look-up process starts from vlan table look-up to determine whether the vid is va lid. if the vid is not valid, the packet will then be dropped and its address will not be learned. if the vid is valid, fid is retrieved for further look-up by the static mac table or dynamic mac table. fid+da is used to determine the destination port. table 3-16 describes the different actions in different situations of da and fid+da in the static mac table and dynamic mac table after the vlan table finishes a look- up action. fid+sa is used for learning purposes. ta b l e 3 - 1 7 also describes learning in the dynamic mac table when the vlan table has done a look-up in the static mac table without a valid entry. table 3-16: fid+da look-up in vlan mode da found in static mac table? use fid flag? fid match? fid+da found in dynamic mac table? action no dont care dont care no broadcast to the membership ports defined in the vlan table bits[11:7]. no dont care dont care yes send to the destination port defined in the dynamic mac address table bits[58:56]. yes 0 dont care dont care send to the destination port(s) defined in the static mac address table bits[52:48]. yes 1 no no broadcast to the membership ports defined in the vlan table bits[11:7]. downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 39 KSZ8795clx advanced vlan features are also supported in KSZ8795clx, such as vlan ingress filtering and discard non pvid defined in bits [6:5] of the port control 2 register . these features can be controlled on a per port basis. 3.6.9 rate limiting support the KSZ8795clx provides a fine resolution hardware rate limiting based on both bps (bit per second) and pps (packet per second). for bps, the rate step is 64 kbps when the rate limit is less than 1mbps rate for 100bt or 10bt, and 640 kbps for 1000. the rate step is 1mbps when the rate limit is more than 1mbps rate for 100bt or 10bt, 10 mbps for 1000. for pps, the rate step is 128 pps (besides the 1st one which is 64 pps) when the rate limit is less than 1mbps rate for 100bt or 10bt, and 1280 pps (except the 1st one of 640 pps) for 1000. the rate step is 1mbps when the rate limit is more than 1.92 kpps rate for 100bt or 10bt, 19.2 kpps for 1000 (refer to table 3-18 ). the pps limiting is bounded by the bps rate for each pps setting. the mapping is shown in the 2nd column of ta b l e 3 - 1 8 . yes 1 no yes send to the destination port defined in the dynamic mac address table bits[58:56]. yes 1 yes dont care send to the destination port(s) defined in the static mac address table bits[52:48]. table 3-17: fid+sa look-up in vlan mode fid+sa found in dynamic mac table? action no the fid+sa will be learned into the dynamic table. yes time stamp will be updated. table 3-18: 10/100/1000 mbps rate selection for the rate limit item bps bound of pps (egress only) 10 mbps 100 mbps 1000 mbps 7d0 7d0 19.2 kpps 10 mbps 19.2 kpps 100 mbps 1.92 mpps 1000 mbps 7d1 - 7d10 7d3, 6, (8x)10 1.92 kpps x code 1mbps x code 1.92 kpps x code 1mbps x code 19.2 kpps x code 10 mbps x code 7d11 - 7d100 7d11 - 7d100 10 mbps 1.92 kpps x code 1mbps x code 19.2 kpps x code 10 mbps x code 7d101 7d102 64 pps 64 kbps 64 pps 64 kbps 640 pps 640 kbps 7d102 7d104 128 pps 128 kbps 128 pps 128 kbps 1280 pps 1280 kbps 7d103 7d108 256 pps 192 kbps 256 pps 192 kbps 2560 pps 1920 kbps 7d104 7d112 384 pps 256 kbps 384 pps 256 kbps 3840 pps 2560 kbps 7d105 7d001 512 pps 320 kbps 512 pps 320 kbps 5120 pps 3200 kbps 7d106 7d001 640 pps 384 kbps 640 pps 384 kbps 6400 pps 3840 kbps 7d107 7d001 768 pps 448 kbps 768 pps 448 kbps 7680 pps 4480 kbps 7d108 7d002 896 pps 512 kbps 896 pps 512 kbps 8960 pps 5120 kbps 7d109 7d002 1024 pps 576 kbps 1024 pps 576 kbps 10240 pps 5760 kbps 7d110 7d002 1152 pps 640 kbps 1152 pps 640 kbps 11520 pps 6400 kbps 7d111 7d002 1280 pps 704 kbps 1280 pps 704 kbps 12800 pps 7040 kbps 7d112 7d002 1408 pps 768 kbps 1408 pps 768 kbps 14080 pps 7680 kbps 7d113 7d003 1536 pps 832 kbps 1536 pps 832 kbps 15360 pps 8320 kbps table 3-16: fid+da look-up in vlan mode (continued) da found in static mac table? use fid flag? fid match? fid+da found in dynamic mac table? action downloaded from: http:///
KSZ8795clx ds00002112a-page 40 ? 2016 microchip technology inc. the rate limit is independently on the receive side and on the transmit side on a per port basis. for 10base-t, a rate setting above 10 mbps means the rate is not limited. on the receive side, the data receive rate for each priority at each port can be limited by setting up ingress rate control registers. on the transmit si de, the data transmit rate for each queue at eac h port can be limited by setting up egress rate control registers. for bps mode, the size of each frame has options to include minimum interframe gap (ifg) or preamble byte, in addition to the data field (from packet da to fcs). 3.6.9.1 ingress rate limit for ingress rate limiting, KSZ8795clx provides options to se lectively choose frames from all types; multicast, broad- cast, and flooded unicast frames via bits [3:2] of the port rate limit control register. the KSZ8795clx counts the data rate from those selected type of fram es. packets are dropped at the ingress port when the data rate exceeds the spec- ified rate limit or the flow control ta kes effect without packet dropped when the ingress rate limit flow control is enabled by the port rate limit control register bit[4]. the ingre ss rate limiting supports the port-based, 802.1p and diffserv- based priorities. the port-based priority is fixed priority 0-3 selection by bits [4:3] of the port control 0 register. the 802.1p and diffserv-based priority can be m apped to priority 0-3 by default of the register 128 and 129. in the ingress rate limit, set register 135 global control 19 bit[3] to enable queue-based rate limit if using 2-queue or 4-queue mode. all related ingress ports and egress port should be split to two-queue or four-queue mode by the port control 9 and control 0 registers. the 4-queue mode will use q0-q3 for priority 0-3 by bits [6:0] of the port register ingress limit con- trol 1-4. the 2-queue mode will use q0-q1 fo r priority 0-1 by bits [6:0] of the port ingress limit control 1-2 registers. the priority levels in the packets of the 8 02.1p and diffserv can be programmed to pr iority 0-3 via the register 128 and 129 for a re-mapping. 3.6.9.2 egress rate limit for egress rate limiting, the leaky bucket algorithm is applie d to each output priority queu e for shaping output traffic. interframe gap is stretched on a per frame base to generat e smooth, non-burst egress traf fic. the throughput of each output priority queue is limited by the egress rate specified by the data rate selection table followed the egress rate limit control registers. if any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the output queue and packet memory. after the memory of the q ueue or the port is used up, packet dropping or flow control will be triggered. as a result of conges tion, the actual egress rate may be domin ated by flow control/dropping at the ingress end, and may be therefore slightly less than the specified egress rate. the egress rate limiting supports the port- based, 802.1p and diffserv-based priorities, th e port-based priority is fixed priority 0-3 selection by bits [4:3] of the port control 0 register. the 802.1p and diffserv-based priority can be mapped to priority 0-3 by default of the register 128 and 129. in the egress rate limit, set register 135 global control 19 bit[3] for queue-based rate limit to be enabled if using two-queue or four-queue mode. all related ingress port s and egress port should be split to 2-queue or 4-queue mode by the port control 9 and control 0 registers. the 4-q ueue mode will use q0-q3 for priority 0-3 by bits [6:0] of the port egress limit control 1-4 regist er. the 2-queue mode will use q0-q1 for priority 0-1 by bits [6:0] of the port egress rate limit control 1-2 register. the priority levels in the packets of the 802.1p and diffserv can be programmed to priority 0-3 by register 128 and 129 for a re-mapping. when the egress rate is limited, just use one queue per po rt for the egress port rate limit. the priority packets will be based upon the data rate selection table (see table 3-18 ). if the egress rate limit uses more than one queue per port for the egress port rate limit, then the highest priority packets will be based upon the data rate selection table for the rate limit exact number. other lower priority packet rates will be lim ited based upon 8:4:2:1 (defau lt) priority ratio, which is based on the highest priority rate. the transmit queue priority ratio is programmable. to reduce congestion, it is good practice to make sure the egress bandwidth exceeds the ingress bandwidth. 7d114 7d003 1664 pps 896 kbps 1664 pps 896 kbps 16640 pps 8960 kbps 7d115 7d003 1792 pps 969 kbps 1792 pps 969 kbps 17920 pps 9690 kbps table 3-18: 10/100/1000 mbps rate selec tion for the rate limit (continued) item bps bound of pps (egress only) 10 mbps 100 mbps 1000 mbps downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 41 KSZ8795clx 3.6.9.3 transmit queue ratio programming in transmit queues 0-3 of the egress port, the default priority ratio is 8:4:2:1. the priority ratio can be programmed by the port control 10, 11, 12, and 13 regi sters. when the transmit rate exceeds the ratio limit in the transmit queue, the transmit rate will be limited by the trans mit queue 0-3 ratio of the port control 10, 11, 12, and 13 registers. the highest priority queue will not be limited. other lower priority queues will be limited based on the transmit queue ratio. 3.6.10 vlan and address filtering to prevent certain kinds of packets that could degrade the quality of t he switch in applications such as voice over internet protocol (voip), the switch provides t he mechanism to filter and map the packets with the following mac addresses and vlan ids. self-address packets unknown unicast packets unknown multicast packets unknown vid packets unknown ip multicast packets the packets sourced from switch itself can be filtered out by enabling self-address filter ing via the global control 18 register bit[6]. the self-addre ss filtering will filter packets on the egress port; self mac address is assigned in the reg- ister 104-109 mac address registers 0-5. the unknown unicast packet filtering can be enabled by the gl obal control register 15 bit[5] and bits[4:0] specify the port map for forwarding. the unknown multicast packet filtering can be enabled by the global control regist er 16 bit[5] and forwarding port map is specified in bits[4:0]. the unknown vid packet filtering can be enabled by global co ntrol register 17 bit[5] with forwarding port map specified in bits[4:0]. the unknown ip multicast packet filtering can be enable by global control register 18 bit[5] with forwarding port map specified in bits[4:0]. those filtering above are global based. 3.6.11 802.1x port-based security ieee 802.1x is a port-based aut hentication protocol. eapol is t he protocol normally used by the authentication process as an uncontrolled port. by receivin g and extracting special eapol frames, the microprocessor (cpu) can control whether the ingress and egress ports should forward packets or not. if a user port wants service from another port (authenticator), it must get approved by the authenticator. the ksz879 5clx detects eapol frames by checking the destination address of the frame. the destination addresses should be either a multicast address as defined in ieee 802.1x (01-80-c2-00-00-03) or an address used in the programmable reserved mult icast address domain with offset - 00-03. once eapol frames are det ected, the frames are forwarded to the cpu so it can send the frames to the authen- ticator server. eventually, the cpu determines whether the requestor is qualified or not based on its mac_source addresses, and frames are ei ther accepted or dropped. when the KSZ8795clx is configured as an authenticator, the po rts of the switch must then be configured for authori- zation. in an authenticator-initiated port authorization, a client is powered up or plugs into the port, and the authenticator port sends an extensible authentication protocol (eap) pdu to the supplicant requesting th e identification of the suppli- cant. at this point in the process, the port on the switch is connected from a physical standpoint; however, the 802.1x process has not authorized the port and no frames are passed from the port on the supplicant into the switching fabric. if the pc attached to the switch did not understand the eap pdu that it was receiving from the switch, it would not be able to send an id and the port would remain unauthorized. in this state, the port would never pass any user traffic and would be as good as disabled. if the client pc is running the 802.1x eap, it would respond to the request with its con- figured id. this could be a user name/password combination or a certificate. after the switch, the authentic ator receives the id from the pc (the supplicant). the KSZ8795clx then passes the id information to an authentication server (radius server) t hat can verify the identification information. the radius server responds to the switch with eith er a success or failure message. if the response is a success, the port will then be authorized and user traffic will be allowed to pass through t he port like any switch port connected to an access device. if the response is a failure, the port will remain unauthoriz ed and, therefore, unused. if there is no response from the server, the port will also remain un authorized and will not pass any traffic. downloaded from: http:///
KSZ8795clx ds00002112a-page 42 ? 2016 microchip technology inc. 3.6.11.1 authentication register and programming model the port authentication control registers define the control of port-based authentication. the per-port authentication can be programmed in these registers. ksz8 795clx provides three modes for impl ementing the ieee 802.1x feature. each mode can be selected by setting the appropriate bits in the port authentication registers. when mode control bits authenciation_mode = 00 (pa ss mode), forced-authorization is enabled and a port is always authorized and does not require any messages from eit her the supplicant or the aut hentication server. this is typically the case when connecting to another switch, a rout er, or a server, and also when connecting to clients that do not support 802.1x. when acl is enabled, all the packets are passed if they miss acl rules, otherwise, acl actions apply. the block mode (when authenciation_mode = 01) is the standard port-based authentication mode. a port in this mode sends eap packets to the supplicant and will not become authorized unless it rece ives a positive response from the authentication server. traffic is bl ocked before authentication to all of the incoming packets, upon authentication, software will switch to pass mode to allow all the incoming packets. in this mode, the source address of incoming pack- ets is not checked. including the eap a ddress, the forwarding map of the enti re reserved multicast addresses need to be configured to be allowed to be forwarded before and afte r authentication in lookup tabl e. when acl is enabled, pack- ets except acl hit are blocked. the third mode is trap mode (when authentication_mode = 11'b). in this mode, all the packets are sent to cpu port. if acl is enabled, the missed packets would be forwarded to the cpu rather than droppe d. all these per port fea- tures can be selected through the port control 5 register, bit[2] is used to enable acl, bits[1:0] is for the modes selected. 3.6.12 acl filtering access control lists (acl) can be created to perform the protocol-independent layer 2 mac, layer 3 ip, or layer 4 tcp/ udp acl filtering that filters incoming et hernet packets based on acl rule table. the feature allows t he switch to filter customer traffic based on the source mac address in the et hernet header, the ip address in the ip header, and the port number and protocol in the tcp header. this function can be performed through mac table and acl rule table. besides multicast filtering handled using entries in the static table, acls can be co nfigured for all routed network protocols to filter the packets of those protocols as the packets pass thr ough the switch. acls can preven t certain traffic from enter- ing or exiting a network. 3.6.12.1 access control lists the KSZ8795clx offers a rule-based acl rule table. the acl rule table is an ordered list of access control entries. each entry specifies certain ru les (a set of matching conditions and action rules) to permit or deny the packet access to the switch fabric. the meaning of permit or deny depend s on the context in which the acl is used. when a packet is received on an interface, the switch compares the fields in the packet against any applied acls to verify that the packet has the permissions required to be forwarded, based on the conditions specified in the lists. the filter tests the packets against the acl entries one-by -one. usually the first match determines whether the router accepts or rejects packets. however, it is allowed to cascade the rules to form more robust and/or stringent requirements for incoming packets. acls allow switch filter ingress traffic based on the so urce, destination mac address and ethernet type in the layer 2 header, the source, and destination ip address in layer 3 header, and port number, protocol in the layer 4 header of a packet. each list consists of three parts: matching field action field processing field the matching field specifies the rules that each packet matche s against and the action field specifies the action taken if the test succeeds against the rules. figure 3-11 shows the format of acl and a description of the individual fields. downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 43 KSZ8795clx matching field md [1:0]: mode there are three modes of operat ion defined in acl. mode 0 disables the cu rrent rule list, mode 1 is qualification rules for layer 2 mac header f iltering, mode 2 is used for layer 3 ip address filtering and mode 3 performs layer 4 tcp port number/protocol filtering. while mode 0 is selected, there will be no action taken. enb [1:0]: enable enables different rules in the current list. - when md = 01 while enb = 00, the 11 bits of the aggregated bit field fr om pm, p, rpe, rp, mm in the action field specify a count value for packets matc hing the mac address and type in the matching fields. the count unit is defined in msb of forward bit field; while = 0, s will be used and while = 1, ms will apply. the 2nd msb of the forward bit determines the algorith m used to generate an interrupt when the counter terminates. when = 0, an 11-bit counter will be loaded with the count value from the acl list and starts count- ing down every unit of time. an interrupt will be generate d when it expires, i.e., t he next qualified packet has not been received within the per iod specified by the value. when = 1, the counter is incremented on every matched packet received and an interrupt is generated while terminal count reach the count value in t he acl list, the count resets thereafter. when enb = 01, the mac address bit field is participati ng in test; when enb = 10, the mac type bit field is used for test; when enb = 11, both the mac address and ty pe are tested against these bit fields in the list. - when md = 10 figure 3-11: acl format downloaded from: http:///
KSZ8795clx ds00002112a-page 44 ? 2016 microchip technology inc. if enb = 01, the ip address and mask or ip protocol is enabled to be tested accordingly. if enb = 10, source and destination addresses are compared. the drop/f orward decision is based on the eq bit setting. - when md = 11 if enb = 00, protocol comparison is enabled. if enb = 01, tcp address comparison is selected. if enb = 10, udp address comparison is selected. if enb = 11, the sequence number of the tcp is compared. s/d: source or destination select - when = 0, the destination address/port is used to compare; and when = 1, the source is chosen. e/q: comparison algorithm - when = 0, a match if they are not equal. when = 1, a match if they are equal. mac address [47:0] - mac source or destination address type [15:0] - mac ether type. ip address [31:0] - ip source or destination address. ip mask [31:0] - ip address mask for group address filtering. max port [15:0], min port [15:0]/se quence number [31:0] - the range of tcp port number or sequence number matching. pc [1:0]: port comparison - when = 00, the comparison is disabled; when = 01, matc hes either one of max or min; when = 10, a match if the port number is in the range of max to min; and when = 11, a match if the port number is out of the range. pro [7:0] - ip protocol to be matched. fme - flag match enable C when = 1, enable tcp flag matching. flag [5:0] - tcp flag to be matched. action field pm [1:0]: priority mode - when = 00, no priority is selected, the priority is det ermined by the qos/classificat ion is used. when = 01, the priority in p bit field is used if it is greater than qos re sult. when = 10, the priority in p bit field is used if it is smaller than qos result. when = 11, the p bit fi eld will replace the priority determined by qos. p [2:0] -priority. rpe: remark priority enable - when = 0, no remarking is necessary. when = 1, the vlan priority bits in the tagged packets are replaced by rp bit field in the list. rp [2:0] - remarked priority. mm [1:0]: map mode - when = 00, no forwarding remapping is necessary. when = 01, the forwarding map in forword is ored with the forwarding map from the look-up table. w hen = 10, the forwarding map in forword is anded with the forwarding map from the look-up table. when = 11, the forwarding map in forword replaces the forwarding map from the look-up table. forward bits[4:0]: forwarding port(s) - each bit indicates the forwarding decision of one port. processing field frn bits[3:0]: first rule number - assign which entry with its action field in 16 entries is used in the rule set. ruleset bits[15:0]: rule set downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 45 KSZ8795clx - group of rules to be qualified, there are 16 entries rule can be assigned to a rule set per port by the two rule- set registers. the rule table allows the rules to be cascaded. there are 16 entries in the rtb. each entry can be a rule on its own, or can be cascaded with other entries to form a rule set. the test result of incoming pack- ets against rule set will be the anded result of all th e test result of incoming packets against the rules included in this rule set. the action of the rule set will be the action of the first rule specified in frn field. the rule with higher priority will have lower index number. or ru le 0 is the highest priority rule and rule 15 is the lowest priority. acl rule table entry is disabled when mode bits are set to 2b00. a rule set (ruleset) is used to select the match results of different rules against incoming packets. these selected match results will be anded to determine whet her the frame matches or not . the conditions of dif- ferent rule sets having the same action will be ored for comparison with frame fields, and the cpu will pro- gram the same action to those rule sets that are to be ored together. for matched rule sets, different rule sets having different actions will be arbitrated or chosen based upon the first rule number (frn) of each rule set. the rule table will be set up with the high priority ru le at the top of the table or with the smaller index. regardless whether the matched rule sets have the same or different action, the hardware will always com- pare the first rule number of different rule sets to determine the final rule set and action. 3.6.12.2 dos attack prevention via acl the acl can provide certain detection/pr otection of the following denial of service (dos) attack types based on rule setting, which can be programmed to drop or not to drop each type of dos packet respectively. example 1 when md = 10, enable = 10, setting eq bit to 1 can determine the drop or forward packets with identical source and destination ip addresses in ipv4/ipv6. example 2 when md = 11, enable = 01/10, setting eq bit to 1 can determine the drop or forward packets with identical source and destination tcp/udp ports in ipv4/ipv6. example 3 when md = 11, enable = 11, sequence number = 0, fme = 1, fmsk = 00101001, flag = xx1x1xx1, setting the eq bit to 1 will drop/forward the all packets with a tcp sequenc e number equal to 0, and flag bit urg = 1, psh = 1 and fin = 1. example 4 when md = 11, enable = 01, max port = 1024, min port = 0, fme = 1, fmsk = 00010010, flag = xxx0xx1x, setting the eq bit to 1 will drop/forward the all packets with a tcp port number 1024, and flag bit urb = 0, syn = 1. acl related registers list as: the register 110 (0x6e), the register 111 (0x6f) and the acl rule tables. downloaded from: http:///
KSZ8795clx ds00002112a-page 46 ? 2016 microchip technology inc. 4.0 device registers the KSZ8795clx device has a rich set of registers available to manage the functionality of the device. access to these registers is via the miim or spi interfaces. figure 4-1 provides a global picture of accessibility via the various interfaces and addressing ranges from the perspective of each interface. the registers within the linear 0x00-0xff address space are all accessible via the spi interface by a cpu attached to that bus. the mapping of the various functions within that linear address space is summarized in table 4-1 . figure 4-1: interface and register mapping table 4-1: mapping of functional areas within the address space register locations device area description 0x00 - 0xff switch control and configuration registe rs which control the over all functionality of the switch, mac, and phys 0x6e - 0x6f indirect control registers registers used to indirectly address and access distinct areas within the device. - management information base (mib) counters - static mac address table - dynamic mac address table - vlan table - pme indirect registers - acl indirect registers - eee indirect registers 0x70 - 0x78 indirect access registers registers used to indirectly address and access four distinct areas within the device. - management information base (mib) counters - static mac address table - dynamic mac address table - vlan table 0xa0 indirect byte access registers this in direct byte register is used to access: - pme indirect registers - acl indirect registers - eee indirect registers switch config registers 00 " 0xff regad 0-5, 1d, 1f miim registers 00h - ffh spi phyad 1, 2, 3, 4 17h - 4fh phy block downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 47 KSZ8795clx 4.1 register map 0x17 - 0x4f phy1 to phy4 miim registers mapping to those port registers address range the same phy registers as specified in ieee 802.3 specification. table 4-2: direct registers address contents 0x00-0x01 family id, chip id, revision id, and start switch registers 0x02-0x0d global control registers 0 C 11 0x0e-0x0f global power-down management control registers 0x10-0x14 port 1 control registers 0 C 4 0x15 port 1 authentication control register 0x16-0x18 port 1 reserved (factory test registers) 0x19-0x1f port 1 control/status registers 0x20-0x24 port 2 control registers 0 C 4 0x25 port 2 authentication control register 0x26-0x28 port 2 reserved (factory test registers) 0x29-0x2f port 2 control/status registers 0x30-0x34 port 3 control registers 0 C 4 0x35 port 3 authentication control register 0x36-0x38 port 3 registered (factory test registers) 0x39-0x3f port 3 control/status registers 0x40-0x44 port 4 control registers 0 C 4 0x45 port 4 authentication control register 0x46-0x48 port 4 reserved (factory test registers) 0x49-0x4f port 4 control/status registers 0x50-0x54 port 5 control registers 0 C 4 0x56-0x58 port 5 reserved (factory test registers) 0x59-0x5f port 5 control/status registers 0x60-0x67 reserved (factory testing registers) 0x68-0x6d mac address registers 0x6e-0x6f indirect access control registers 0x70-0x78 indirect data registers 0x79-0x7b reserved (factory testing registers) 0x7c-0x7d global interrupt and mask registers 0x7e-0x7f acl interrupt status and control registers 0x80-0x87 global control registers 12 C 19 0x88 switch self-test control register 0x89-0x8f qm global control registers 0x90-0x9f global tos priority control registers 0 - 15 0xa0 global indirect byte register 0xa0-0xaf reserved (factory testing registers) 0xb0-0xbe port 1 control registers table 4-1: mapping of functional areas within the address space (continued) register locations device area description downloaded from: http:///
KSZ8795clx ds00002112a-page 48 ? 2016 microchip technology inc. 0xbf reserved (factory testing register): transmit queue remap base register 0xc0-0xce port 2 control registers 0xcf reserved (factory testing register) 0xd0-0xde port 3 control registers 0xdf reserved (factory testing register) 0xe0-0xee port 4 control registers 0xef reserved (factory testing register) 0xf0-0xfe port 5 control registers 0xff reserved (factory testing register) table 4-3: global registers address name description mode default register 0 (0x00): chip id0 7 ? 0 family id chip family. ro 0x87 register 1 (0x01): chip id1/start switch 7 ? 4 chip id 0x9 = 8795 ro 0x9 3 ? 1 revision id ro 0x0 0 start switch 1 = start the switch function of the chip. 0 = stop the switch function of the chip. r/w 1 register 2 (0x02): global control 0 7 new back-off enable new back-off algorithm designed for unh 1 = enable 0 = disable r/w 0 6 global soft reset enable global software reset 1 = enable to reset all fsm and data path (not con- figuration). 0 = disable reset. note : this reset will stop to receive packets if it is being in the traffic. all registers keep their configu- ration values. r/w 0 5 flush dynamic mac table flush the entire dynamic mac table for rstp. this bit is self- clear (sc). 1 = trigger the flush dynamic mac table operation. 0 = normal operation. note : all the entries associated with a port that has its learning capability being turned off (learning dis- able) will be flushed. if you want to flush the entire table, all ports learning capability must be turned off. r/w (sc) 0 table 4-2: direct registers (continued) address contents downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 49 KSZ8795clx 4 flush static mac table flush the matc hed entries in static mac table for rstp 1 = trigger the flush static mac table operation. 0 = normal operation. note : the matched entry is defined as the entry in the forwarding ports field contains a single port and mac address with unicast. this port, in turn, has its learning capability being turned off (learning disable). per port, multiple entries can be qualified as matched entries. r/w (sc) 0 3 reserved n/a dont change ro 1 2 reserved n/a dont change ro 1 1 unh mode 1 = the switch will drop packets with 0x8808 in the t/l filed, or da = 01-80-c2-00-00-01. 0 = the switch will drop packets qualified as flow control packets. r/w 0 0 link change age 1 = link change from link to no link will cause fast aging (<800 s) to age address table faster. after an age cycle is complete, the age logic will return to normal (3 00 75 seconds). note : if any port is unplugged, all addresses will be automatically aged out. r/w 0 register 3 (0x03): global control 1 7 reserved n/a dont change. ro 0 6 2kb packet support 1 = enable 2kb packet support. 0 = disable 2kb packet support. r/w 0 5 ieee 802.3x transmit flow control disable 0 = enables transmit flow control based on an result. 1 = will not enable transmit flow control regardless of the an result. r/w 0 4 ieee 802.3x receive flow control disable 0 = enables receive flow control based on an result. 1 = will not enable receive flow control regardless of the an result. note : bit[5] and bit[4] default values are controlled by the same pin, but they can be programmed independently. r/w 0 3 frame length field check 1 = check frame length fiel d in the ieee packets. if the actual length does not match, the packet will be dropped (for l/t <1500). r/w 0 2 aging enable 1 = enable aging function in the chip. 0 = disable aging function. r/w 1 1 fast-age enable 1 = turn on fast aging (800 s). r/w 0 0 aggressive back-off enable 1 = enable more aggressive back-off algorithm in half duplex mode to enhance performance. this is not in the ieee standard. r/w 0 table 4-3: global registers (continued) address name description mode default downloaded from: http:///
KSZ8795clx ds00002112a-page 50 ? 2016 microchip technology inc. register 4 (0x04): global control 2 7 unicast port-vlan mismatch discard this feature is used for port vlan (described in port control 1 register). 1 = all packets cannot cross vlan boundary. 0 = unicast packets (excluding unknown/multicast/ broadcast) can cross vlan boundary. note : when mirroring is enabled, the single-desti- nation packets will be dropped if its mirrored to another port. r/w 1 6 multicast storm protection disable 1 = broadcast storm protection does not include multicast packets. only da = ffffffffffff packets will be regulated. 0 = broadcast storm protection includes da = ffffffffffff and da[40] = 1 packet. r/w 1 5 back pressure mode 1 = carrier-sense-based back pressure is selected. 0 = collision-based back pressure is selected. r/w 1 4 flow control and back pressure fair mode 1 = fair mode is selected. in this mode, if a flow control port and a non-flow control port talk to the same destination port, then packets from the non- flow control port may be dropped. this is to prevent the flow control port from being flow controlled for an extended period of time. 0 = in this mode, if a flow control port and a non- flow control port talk to the same destination port, the flow control port will be flow controlled. this may not be fair to the flow control port. r/w 1 3n o excessive collision drop 1 = the switch will not drop packets when 16 or more collisions occur. 0 = the switch will drop packets when 16 or more collisions occur. r/w 0 2 reserved n/a dont change. ro 0 1 legal maximum packet size check disable 1 = enables acceptance of packet sizes up to 1536 bytes (inclusive). 0 = 1522 bytes for tagged packets (not including packets with stpid from cpu to ports 1-4), 1518 bytes for untagged packets. any packets larger than the specified value will be dropped. r/w 0 0 reserved n/a ro 0 register 5 (0x05): global control 3 7 802.1q vlan enable 1 = 802.1q vlan mode is turned on. vlan table needs to be set up before the operation. 0 = 802.1q vlan is disabled. r/w 0 6 igmp snoop enable on switch port 5 sw5-gmii/ rgmii/mii/rmii interface 1 = igmp snoop enabled. all the igmp packets will be forwarded to the processor via switch port 5 gmii/rgmii/mii/rmii interface. 0 = igmp snoop disabled. r/w 0 5 ? 1 reserved n/a dont change. ro 00000 table 4-3: global registers (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 51 KSZ8795clx 0 sniff mode select 1 = enables rx and tx sniff (both source port and destination port need to match). 0 = enables rx or tx sniff (either source port or destination port need to match). note : default is used to implement rx only sniff. r/w 0 register 6 (0x06): global control 4 7 switch sw5-mii/rmii back pressure enable 1 = enable half-duplex back pressure on the switch mii/rmii interface. 0 = disable back pressure on the switch mii inter- face. r/w 0 6 switch sw5-mii/rmii half-duplex mode 1 = enable mii/rmii interface half-duplex mode. 0 = enable mii/rmii interface full-duplex mode. r/w 0 5 switch sw5-mii/rmii flow control enable 1 = enable full-duplex flow control on the switch mii/rmii interface. 0 = disable full-duplex flow control on the switch mii/rmii interface. r/w 0 4 switch sw5-mii/rmii speed 1 = the switch sw5-mii/rmii is in 10 mbps mode. 0 = the switch sw5-mii/rmii is in 100 mbps mode. r/w 0 3 null vid replacement 1 = replace nu ll vid with port vid (12 bits). 0 = no replacement for null vid. r/w 0 2 ? 0 broadcast storm protec- tion rate bit[10:8] this register, along with the next register, deter- mines how many 64 byte blocks of packet data are allowed on an input port in a preset period. the period is 50 ms for 100bt or 500 ms for 10bt. the default is 1%. r/w 000 register 7 (0x07): global control 5 7 ? 0 broadcast storm protec- tion rate bits[7:0] this register, along with the previous register, determines how many 64- byte blocks of packet data are allowed on an input port in a preset period. the period is 50 ms for 100bt or 500 ms for 10bt. the default is 1%. note :148,800 frames/sec 50 ms/interval 1% = 74 frames/interval (approx.) = 0x4a. r/w 0x4a register 8 (0x08): global control 6 mib control 7 flush counter 1 = all the mib co unter of enabled port(s) will be reset to 0. this bit is self-cleared after the operation finishes. 0 = no reset of the mib counter. r/w (sc) 0 6 freeze counter 1 = enabled port(s) will stop counting. 0 = enabled port(s) will not stop counted. r/w 0 5 reserved n/a dont change. ro 0 4 ? 0 control enable 1 = enable flush and freeze for each port. bit[4] is for port 5 flush + freeze. bit[3] is for port 4 flush + freeze. bit[2] is for port 3 flush + freeze. bit[1] is for port 2 flush + freeze. bit[0] is for port 1 flush + freeze. 0 = disable flush and freeze. r/w 0 table 4-3: global registers (continued) address name description mode default downloaded from: http:///
KSZ8795clx ds00002112a-page 52 ? 2016 microchip technology inc. register 9 (0x09): global control 7 7 - 0 factory testing n/a dont change ro 0x40 register 10 (0x0a): global control 8 7 - 0 factory testing n/a dont change ro 0x00 register 11 (0x0b): global control 9 7 reserved n/a dont change ro 0 6 port 5 sw5- rmii refer- ence clock edge select select the data sampling edge of the sw5- rmii reference clock: 1 = data sampling on the negative edge of ref- clk. 0 = data sampling on the positive edge of refclk (default). r/w 0 5 ? 4 led mode programmable led output to indicate ports activ- ity/status using 2 bits of the control register. led is on (active) when the output is low; the led is off (inactive) when the output is high. link = led on; act = led blink; link/act = led on/blink. speed = led on (100bt); led off (10bt); led blink (1000bt reserved). duplex = led on (full duplex); led off (half duplex). r/w 00 3 reserved n/a dont change. ro 0 2 reserved n/a dont change. ro 0 1 refclko enable 1 = enable refclko pin clock output 0 = disable refclko pin clock output. strap-in option: led2_0 pu = refclk_o (25 mhz) is enabled. (default) pd = refclk_o is disabled note : this is an additional clock; this clock can save an oscillator if system needs this clock source. if the system doesnt need this 25 mhz clock source, which should be disabled. r/w 0 0 spi read sampling clock edge select select the spi clock edge for sampling spi read data. 1 = trigger on the rising edge of spi clock (for higher speed spi) 0 = trigger on the falling edge of spi clock. r/w 0 register 12 (0x0c): global control 10 7 ? 6 reserved reserved ro 01 5 ? 2 reserved n/a dont change. ro 0001 table 4-3: global registers (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 53 KSZ8795clx 4.2 port registers the following registers are used to enable features that ar e assigned on a per port basis. the register bit assignments are the same for all ports, but the address for each port is different, as indicated. 1 tail tag enable tail tag feature is applied for port 5 only. 1 = insert 1 byte of data right before fcs. 0 = do not insert. r/w 0 0 pass flow control packet 1 = switch will not filter 802.3x flow control pack- ets. 0 = switch will filter 802.3x flow control packets. r/w 0 register 13 (0x0d): global control 11 7 C 0 factory te s t i n g n/a dont change. ro 00000000 register 14 (0x0e): power-down management control 1 7 ? 6 reserved n/a dont change. ro 00 5 pll power-down pll power-down enable: 1 = enable 0 = disable note : it occurs in the energy detect mode (edpd mode) r/w 0 4 C 3 power management mode select power management mode : 00 = normal mode (d0) 01 = energy detection mode (d2) 10 = soft power-down mode (d3) 11 = reserved note : rc means read clear. r/w (rc) 00 2 ? 0 reserved n/a dont change. ro 000 register 15 (0x0f): power-down management control 2 7 - 0 go_sleep_time [7:0] when the energy -detect mode is on, this value is used to control the mini mum period that the no energy event has to be detected consecutively before the device enters the low power state. the unit is 20 ms. the default of go_sleep time is 1.6 seconds (80 dec 20 ms). r/w 01010000 table 4-4: port registers address name description mode default register 16 (0x10): port 1 control 0 register 32 (0x20): port 2 control 0 register 48 (0x30): port 3 control 0 register 64 (0x40): port 4 control 0 register 80 (0x50): port 5 control 0 7 broadcast storm protection enable 1 = enable broadcast storm protection for ingress packets on the port. 0 = disable broadcast storm protection. r/w 0 table 4-3: global registers (continued) address name description mode default downloaded from: http:///
KSZ8795clx ds00002112a-page 54 ? 2016 microchip technology inc. 6 diffserv priority classification enable 1 = enable diffserv priori ty classification for ingress packets on port. 0 = disable diffserv function. r/w 0 5 802.1p priority classification enable 1 = enable 802.1p priority classification for ingress packets on port. 0 = disable 802.1p priority classification for ingress packets on port. r/w 0 4 C 3 port-based priority classification enable 00 = ingress packets on port will be classified as priority 0 queue if diffserv or 802.1p classifica- tion is not enabled or fails to classify. 01 = ingress packets on port will be classified as priority 1 queue if diffserv or 802.1p classifica- tion is not enabled or fails to classify. 10 = ingress packets on port will be classified as priority 2 queue if diffserv or 802.1p classifica- tion is not enabled or fails to classify. 11 = ingress packets on port will be classified as priority 3 queue if diffserv or 802.1p classifica- tion is not enabled or fails to classify. note : diffserv, 802.1p and port priority can be enabled at the same time. the ored result of 802.1p and dscp overwrites the port priority. r/w 00 2 tag insertion 1 = when packets are output on the port, the switch will add 802.1q tags to packets without 802.1q tags when received. the switch will not add tags to packets already tagged. the tag inserted is the ingress ports port vid. 0 = disable tag insertion. r/w 0 1 tag removal 1 = when packets are output on the port, the switch will remove 802.1q tags from packets with 802.1q tags when received. the switch will not modify packets received without tags. 0 = disable tag removal. r/w 0 0 two queues split enable this bit[0] in registers16/32/48/64/80 should be in combination with regist ers177/193/209/225/241 bit[1] for ports 1 ? 5. this will select the split of 1, 2, and 4 queues: for port 1, register 177 bit[1], register 16 bit[0]: 11 = reserved 10 = the port output queue is split into four priority queues or if map 802.1p to priority 0 ? 3 mode. 01 = the port output queue is split into two priority queues or if map 802.1p to priority 0 ? 3 mode. 00 = single output queue on the port. there is no priority differentiation even though packets are classified into high or low priority. r/w 0 table 4-4: port registers (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 55 KSZ8795clx register 17 (0x11): port 1 control 1 register 33 (0x21): port 2 control 1 register 49 (0x31): port 3 control 1 register 65 (0x41): port 4 control 1 register 81 (0x51): port 5 control 1 7 sniffer port 1 = port is designated as sniffer port and will trans- mit packets that are monitored. 0 = port is a normal port. r/w 0 6 receive sniff 1 = all the packets received on the port will be marked as monitored packets and forwarded to the designated sniffer port. 0 = no receive monitoring. r/w 0 5 transmit sniff 1 = all the packets transmitted on the port will be marked as monitored packets and forwarded to the designated sniffer port. 0 = no transmit monitoring. r/w 0 4 ? 0 port vlan membership defines the ports port vlan membership. bit[4] stands for port 5, bit[3] stands for port 4, bit[2] stands for port 3, bit[1] stands for port 2, bit[0] stands for port 1. the port can only communicate within the member- ship. a 1 includes a port in the membership; a 0 excludes a port in the membership. r/w 0x1f register 18 (0x12): port 1 control 2 register 34 (0x22): port 2 control 2 register 50 (0x32): port 3 control 2 register 66 (0x42): port 4 control 2 register 82 (0x52): port 5 control 2 7 user priority ceiling 1 = if packet s u ser priority field is greater than the user priority field in the port default tag regis- ter, replace the packets user priority field with the user priority field in the port default tag register control 3. 0 = no replace packets priority filed with port default tag priority filed of the port control 3 regis- ter bits[7:5]. r/w 0 6 ingress vlan filtering. 1 = the switch will discard packets whose vid port membership in vlan table bits[11:7] does not include the ingress port. 0 = no ingress vlan filtering. r/w 0 5 discard non-pvid packets 1 = the switch will discard packets whose vid does not match ingress port default vid. 0 = no packets will be discarded. r/w 0 4 force flow control 1 = enables rx and tx flow control on the port, regardless of the an result. 0 = flow control is enabled based on the an result (default) r/w 0 3 back pressure enable 1 = enable port half-duplex back pressure. 0 = disable port half-duplex back pressure. r/w 0 2 transmit enable 1 = enable packet transmission on the port. 0 = disable packet transmission on the port. r/w 1 table 4-4: port registers (continued) address name description mode default downloaded from: http:///
KSZ8795clx ds00002112a-page 56 ? 2016 microchip technology inc. 1 receive enable 1 = enable packet reception on the port. 0 = disable packet reception on the port. r/w 1 0 learning disable 1 = disable switch address learning capability. 0 = enable switch address learning. r/w 0 register 19 (0x13): port 1 control 3 register 35 (0x23): port 2 control 3 register 51 (0x33): port 3 control 3 register 67 (0x43): port 4 control 3 register 83 (0x53): port 5 control 3 7 ? 0 default tag [15:8] ports default tag, containing: 7 ? 5: user priority bits 4: cfi bit 3 ? 0: vid[11:8] r/w 0 register 20 (0x14): port 1 control 4 register 36 (0x24): port 2 control 4 register 52 (0x34): port 3 control 4 register 68 (0x44): port 4 control 4 register 84 (0x54): port 5 control 4 7 ? 0 default tag [7:0] default port 1s tag, containing: 7 ? 0: vid[7:0] r/w 1 registers 19 and 20 (and those corresponding to other ports) serve two purposes: - associated with the ingress untagged packets and used for egress tagging. - default vid for the ingress untagged or null-vid-tagged packets and used for address look-up. register 21 (0x15): port 1 control 5 register 37 (0x25): port 2 control 5 register 53 (0x35): port 3 control 5 register 69 (0x45): port 4 control 5 register 85 (0x55): port 5 control 5 7 ? 3 reserved n/a dont change. ro 00000 2 acl enable 1 = enable acl 0 = disable acl r/w 0 1 ? 0 authentication_- mode these bits control port-based authentication: 00, 10 = authentication disable, all traffic is allowed (forced-authorized), if ac l is enabled, pass all traf- fic if acl missed 01 = authentication enabled, a ll traffic is blocked, if acl is enabled, traffic is blocked if acl missed 11 = authentication enabled, all traffic is trapped to cpu port, if acl is enabled, traffic is trapped to port 5 cpu port only if acl missed. r/w 00 register 22 (0x16): reserved register 38 (0x26): reserved register 54 (0x36): reserved register 70 (0x46): reserved register 86 (0x56): port 5 interface control 6 7 rmii_clk_sel port 5 sw5-rmii mode select 1 = rmii uses internal clock (clock mode) 0 = rmii uses external clock (normal mode) strap-in option: led2_1 pu = sw5-rmii is in the clock mode (default) pd = sw5-rmii is in the normal mode. note : this pin has an internal pull-up r/w 1 table 4-4: port registers (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 57 KSZ8795clx 6 is_1gbps 1 = 1gbps is chosen for port 5 in gmii/rgmii mode. 0 = 10/100 mbps is chosen for port 5 in gmii/ rgmii mode. strap-in option: led1_0 pu = 1gbps in sw5-gmii/rgmii mode (default) pd = 10/100 mbps in sw5-gmii/rgmii mode note : this pin has an internal pull-up. use bit[4] of the register 6, global control 4 to set for 10 or 100 speed in 10/100 mbps mode. r/w 1 5 reserved n/a dont change. ro 1 4 rgmii internal delay (id) ingress enable enable ingress rgmii-id mode 1 = ingress rgmii-id enabled. an internal delay is added to ingress clock input. 0 = no delay is added, only clock to data skew applied. note: if rgmii connection partner transmit data to clock skew is in standard spec 0.5 ns without delay inserted on pcb, then set bit [4] =1 will enable an ingress delay to meet the input skew min 1ns to max 2.6 ns requirement (the clock trace should be equal length with data traces in pcb lay- out) . r/w 0 3 rgmii internal delay (id) egress enable enable egress rgmii-id mode 1 = egress rgmii-id enabled. an internal delay is added to egress clock output. 0 = no delay is added, only clock to data skew applied. note: if setting bit [3] = 1, rgmii transmit clock adds an internal egress delay to add min 1ns data to clock skew to receive side, then the receiving side may or may not add any internal delay to meet its own receiving timing requirement. (the clock trace should be equal length with data traces in pcb layout if no additional external skew on clock is needed). r/w 1 2 gmii/mii mode select port 5 gmac5 sw5-gmii/mii mode select 1 = gmii/mii is in gmac/mac mode (default). 0 = gmii/mii is in gphy/phy mode. strap-in option: led2_1 pu = gmii/mii is in gmac/mac mode. (default) pd = gmii/mii is in gphy/phy mode. note : when set gmac5 sw5-gmii to gphy mode, the crs and col pins will change from the input to output. when set sw5-mii to phy mode, the crs, col, rxc and txc pins will change from the input to output. r/w 1 table 4-4: port registers (continued) address name description mode default downloaded from: http:///
KSZ8795clx ds00002112a-page 58 ? 2016 microchip technology inc. 1 ? 0 interface mode select note : this is for port 5 sw5-gmii/rgmii/mii/ rmii these bits select the interface type and mode for switch port 5 (sw5). port 5 mode select: 00 = mii 01 = rmii 10 = gmii 11 = rgmii. strap-in option: led3[1:0] 00 = mii 01 = rmii 10 = gmii 11 = rgmii (default) note : these pins have internal pull-ups. r/w 11 register 23 (0x17): port 1 control 7 register 39 (0x27): port 2 control 7 register 55 (0x37): port 3 control 7 register 71 (0x47): port 4 control 7 register 87 (0x57): reserved ( note 4-1 ) 7 ? 6 reserved n/a dont change. ro 00 5 ? 4 advertised_flow_con- trol _capability these bits indicate that the KSZ8795clx has implemented both the optional mac control sub- layer and the pause functi on as specified in ieee clause 31 and annex 31b for full duplex operation independent of rate and medium. 00 = no pause 01 = symmetric pause 10 = asymmetric pause toward link partner toward link partner 11 = both symmetric pause and asymmetric pause toward local devices bit[5] indicates that asymmetric pause is sup- ported. the value of bit[4] when bit[5] is set indi- cates the direction of the pause frames that are supported for flow across the link. asymmetric pause configuration results in independent enabling of the pause receive and pause trans- mit functions as defin ed by ieee annex 31b. r/w 11 3 advertised 100bt full- duplex capability 1 = advertise 100bt full-duplex capability. 0 = suppress 100bt full-duplex capability from transmission to link partner. r/w 1 2 advertised 100bt half- duplex capability 1 = advertise 100bt half-duplex capability. 0 = suppress 100bt half-duplex capability from transmission to link partner. r/w 1 1 advertised 10bt full- duplex capability 1 = advertise 10bt full-duplex capability. 0 = suppress 10bt full-duplex capability from transmission to link partner. r/w 1 0 advertised 10bt half- duplex capability 1 = advertise 10bt half-duplex capability. 0 = suppress 10bt half-duplex capability from transmission to link partner. r/w 1 table 4-4: port registers (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 59 KSZ8795clx register 24 (0x18): port 1 status 0 register 40 (0x28): port 2 status 0 register 56 (0x38): port 3 status 0 register 72 (0x48): port 4 status 0 register 88 (0x58): reserved 7 - 6 reserved n/a dont change. ro 0000 5-4 partner_flow_control_- capable these bits indicate the partner capability for both the optional mac control sub-layer and the pause function as specified in ieee clause 31 and annex 31b for full duplex operation independent to rate and medium. 00 = no pause 01 = symmetric pause 10 = asymmetric pause toward link partner toward link partner 11 = both symmetric pause and asymmetric pause toward local devices ro 00 3 partner 100bt full- duplex capability 1 = link partner 100bt full-duplex capable. 0 = link partner not 100bt full-duplex capable. ro 0 2 partner 100bt half- duplex capability 1 = link partner 100bt half-duplex capable. 0 = link partner not 100bt half-duplex capable. ro 0 1 partner 10bt full- duplex capability 1 = link partner 10bt full-duplex capable. 0 = link partner not 10bt full-duplex capable. ro 0 0 partner 10bt half- duplex capability 1 = link partner 10bt half-duplex capable. 0 = link partner not 10bt half-duplex capable. ro 0 register 25 (0x19): port 1 status 1 register 41 (0x29): port 2 status 1 register 57 (0x39): port 3 status 1 register 73 (0x49): port 4 status 1 register 89 (0x59): reserved ( note 4-1 ) 7 hp_mdix 1 = hp auto mdi/mdi-x mode 0 = microchip auto mdi/mdi-x mode r/w 1 6 factory testing n/a dont change. ro 0 5 polrvs 1 = polarity is reversed 0 = polarity is not reversed ro 0 4 transmit flow control enable 1 = transmit flow control feature is active 0 = transmit flow control feature is inactive ro 0 3 receive flow control enable 1 = receive flow control feature is active 0 = receive flow control feature is inactive ro 0 2 operation speed 1 = link speed is 100 mbps 0 = link speed is 10 mbps ro 0 1 operation duplex 1 = link duplex is full 0 = link duplex is half ro 0 0 reserved n/a dont change. ro 0 table 4-4: port registers (continued) address name description mode default downloaded from: http:///
KSZ8795clx ds00002112a-page 60 ? 2016 microchip technology inc. register 26 (0x1a): port 1 phy control 8 register 42 (0x2a): port 2 phy control 8 register 58 (0x3a): port 3 phy control 8 register 74 (0x4a): port 4 phy control 8 register 90 (0x5a): reserved ( note 4-1 ) 7 cdt 10m short note : cdt means cable diagnostic test 1 = less than 10 meter short ro 0 6 ? 5 cdt_result 00 = normal condition 01 = open condition detected in cable 10 = short condition detected in cable 11 = cable diagnostic test has failed ro 00 4 cdt_enable 1 = enable cable diagnostic test. after cdt test has completed, this bit will be self-cleared. 0 = indicates that the cable diagnostic test (if enabled) has indicate cable diagnostic test. r/w (sc) 0 3 force_link 1 = force link pass 0 = normal operation r/w 0 2 pwrsave 1 = enable power saving 0 = disable power saving r/w 0 1 remote loopback 1 = perform remote loopback, loopback on port 1 as follows: port 1 (reg. 26, bit[1] = 1) start : rxp1/rxm1 (port 1) loopback: pmd/pma of port 1s phy end: txp1/txm1 (port 1) setting reg. 42, 58, 74 bit[1] = 1 will perform remote loopback on ports 2, 3, 4. 0 = normal operation. r/w 0 0 cdt_fault_count[8] bit[8] of cdt fault count distance to the fault. its approximately 0.4 cdt_fault_count[8:0]. ro 0 register 27 (0x1b): port 1 linkmd result register 43 (0x2b): port 2 linkmd result register 59 (0x3b): port 3 linkmd result register 75 (0x4b): port 4 linkmd result register 91 (0x5b): reserved 7 ? 0 cdt_fault_count[7:0] bits[7:0] of cdt fault count distance to the fault. its approximately 0.4m cdt_fault_count[8:0] ro 0x00 table 4-4: port registers (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 61 KSZ8795clx register 28 (0x1c): port 1 control 9 register 44 (0x2c): port 2 control 9 register 60 (0x3c): port 3 control 9 register 76 (0x4c): port 4 control 9 register 92 (0x5c): reserved ( note 4-1 ) 7 disable auto-negotiation 1 = disable auto-negotiation. speed and duplex are decided by bits [6:5] of the same register. 0 = auto-negotiation is on. r/w 0 6 forced speed 1 = forced 100bt if auto-negotiation is disabled (bit[7]). 0 = forced 10bt if auto-negotiation is disabled (bit[7]). r/w 1 5 forced duplex 1 = forced full-duplex if (1) an is disabled or (2) an is enabled but failed. 0 = forced half-duplex if (1) an is disabled or (2) an is enabled but failed (default). r/w 0 4 ? 0 reserved n/a dont change. ro 0x1f register 29 (0x1d): port 1 control 10 register 45 (0x2d): port 2 control 10 register 61 (0x3d): port 3 control 10 register 77 (0x4d): port 4 control 10 register 93 (0x5d): reserved ( note 4-1 ) 7 led off 1 = turn off all ports leds (ledx_2, ledx_1, ledx_0 pins, where x is the port number). these pins will be driven high if this bit is set to one. 0 = normal operation. r/w 0 6 txids 1 = disable ports transmitter. 0 = normal operation. r/w 0 5 restart an 1 = restart auto-negotiation. 0 = normal operation. r/w (sc) 0 4 reserved n/a dont change ro 0 3 power down 1 = power-down. 0 = normal operation. r/w 0 2 disable auto mdi/mdi-x 1 = disable auto-mdi/mdix function. 0 = enable auto-mdi/mdix function. r/w 0 1 forced mdi 1 = if auto-mdi/mdix is disabled, force phy into mdi mode. 0 = mdi-x mode. r/w 0 0 mac loopback 1 = perform mac loopback. loop back path is as follows: e.g., set port 1 mac loopback (reg. 29, bit[0] = (1), use port 2 as monitor port. the packets will transfer. start: port 2 receiving (also can start to receive packets from ports 3, 4, 5). loop-back: port 1s mac. end: port 2 transmitting (also can end at port 3, 4, 5 respectively). setting reg. 45, 61, 77, 93, bit[0] = 1 will perform mac loopback on port 2, 3, 4, 5 respectively. 0 = normal operation. r/w 0 table 4-4: port registers (continued) address name description mode default downloaded from: http:///
KSZ8795clx ds00002112a-page 62 ? 2016 microchip technology inc. note 4-1 port control 7 - 11 and port status 1 - 3 conten ts can be accessed by the mdc/mdio interface via the standard miim registers. register 30 (0x1e): port 1 status 2 register 46 (0x2e): port 2 status 2 register 62 (0x3e): port 3 status 2 register 78 (0x4e): port 4 status 2 register 94 (0x5e): reserved ( note 4-1 ) 7 mdix status 1 = mdi. 0 = mdi-x. ro 0 6 auto-negotiation done 1 = auto-negotiation done. 0 = auto-negotiation not done. ro 0 5 link good 1 = link good. 0 = link not good. ro 0 4 ? 0 reserved n/a dont change. ro 00000 register 31 (0x1f): port 1 control 11 and status 3 register 47 (0x2f): port 2 control 11 and status 3 register 63 (0x3f): port 3 control 11 and status 3 register 79 (0x4f): port 4 control 11 and status 3 register 95 (0x5f): reserved ( note 4-1 ) 7 phy loopback 1 = perform phy loopback. loop back path is as follows: example ? set port 1 phy loopback (reg. 31, bit[7] = (1) use the port 2 as monitor port. the packets will transfer. start: port 2 receiving (also can start from port 3, 4, 5). loopback: pmd/pma of port 1s phy end: port 2 transmitting (also can end at ports 3, 4, 5 respectively). setting reg. 47, 63, 79, 95, bit[7] = 1 will perform phy loopback on port 2, 3, 4, 5 respectively. 0 = normal operation. r/w 0 6 reserved n/a dont change ro 0 5 phy isolate 1 = electrical isolat ion of phy from the internal mii and tx+/tx ? . 0 = normal operation. r/w 0 4 soft reset 1 = phy soft rese t. this bit is self-clearing. 0 = normal operation. r/w (sc) 0 3 force link 1 = force link in the phy. 0 = normal operation r/w 0 2 ? 0 port operation mode indication indicate the current state of port operation mode: 000 = reserved 001 = still in auto-negotiation 010 = 10base-t half duplex 011 = 100base-tx half duplex 100 = reserved 101 = 10base-t full duplex 110 = 100base-tx full duplex 111 = reserved ro 001 table 4-4: port registers (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 63 KSZ8795clx 4.3 advanced control registers registers 104 to 109 define the switching engines mac addr ess. this 48-bit address is used as the source address in mac pause control frames. use registers 110 and 111 to read or write data to the stat ic mac address table, vlan table, dynamic address table, pme registers, acl tables, eee registers and the mib counters. table 4-5: advanced control registers 104 - 109 address name description mode default register 104 (0x68): mac address register 0 7 - 0 maca[47:40] r/w 0x00 register 105 (0x69): mac address register 1 7 - 0 maca[39:32] r/w 0x10 register 106 (0x6a): mac address register 2 7 - 0 maca[31:24] r/w 0xa1 register 107 (0x6b): mac address register 3 7 - 0 maca[23:16] r/w 0xff register 108 (0x6c): mac address register 4 7 - 0 maca[15:8] r/w 0xff register 109 (0x6d): mac address register 5 7 - 0 maca[7:0] r/w 0xff table 4-6: advanced control registers 110 - 111 address name description mode default register 110 (0x6e): indirect access control 0 7 - 5 eee/acl/ pme indirect register function select 000 = indirect mode is used for table select in bits [3:2]. while these bits are not equal 000, bits [3:2] are used for 2 additional msb address bits. 001 = global and port base eee registers are selected, port count is specified in 4 msb indirect address bits and 8 bits register pointer is specified in 8 lsb indirect address bits. 010 = port-base acl registers are selected, port count is specified in 4 msb indirect address bits and register pointer is specified in 8 lsb indirect address bits. 011 = reserved 100 = pme control registers are selected. 101 = linkmd cable diagnosis used. (see example in linkmd cable diagnostics sub-section). r/w 000 4 read high write low 1 = read cycle. 0 = write cycle. r/w 0 downloaded from: http:///
KSZ8795clx ds00002112a-page 64 ? 2016 microchip technology inc. note 4-2 write to register 111 will trigger a command. read or write access is decided by bit[4] of register 110. indirect data registers 112-120 are us ed for table of static, vlan, dynamic table, pme, eee, ac l and mib counter. 3 - 2 table select or indirect address [11:10] if bits [6:5] = 00, then 00 = static mac address table selected. 01 = vlan table selected. 10 = dynamic address table selected. 11 = mib counter selected. if bits [6:5] not equal 00, then these are indirect address [11:10] that is msb of indirect address, bits[11:8] of the indirect address may be served as port address, and bits[7:0] as register address. note: 1. the register 110 bits[3:0] are used for the indi- rect address bits[11:8] 4 msb bits, the four bits are used for the port indirect registers as well. 0000 = global indirect registers 0001 = port 1 indirect registers 0010 = port 2 indirect registers 0011 = port 3 indirect registers 0100 = port 4 indirect registers 0101= port 5 indirect registers 2. the register 111 bits[7:0] are used for the indi- rect address bits of 8 lsb for indirect register address spacing. r/w 00 1 - 0 indirect address [9:8] bits [9:8] of indirect address. r/w 00 register 111 (0x6f): indirect access control 1 ( note 4-2 ) 7 - 0 indirect address [7:0] bits[7:0] of indirect address. r/w 00000000 table 4-7: advanced control registers 112 - 120 address name description mode default register 112 (0x70): indirect data register 8 7 - 0 indirect data [71:64] bits[71:64] of indire ct data. r/w 00000000 register 113 (0x71): indirect data register 7 7 - 0 indirect data [63:56] bits[63:56] of indire ct data. r/w 00000000 register 114 (0x72): indirect data register 6 7 - 0 indirect data [55:48] bits[55:48] of indire ct data. r/w 00000000 register 115 (0x73): indirect data register 5 7 - 0 indirect data [47:40] bits[47:40] of indire ct data. r/w 00000000 register 116 (0x74): indirect data register 4 7 - 0 indirect data [39:32] bits[39:32] of indire ct data. r/w 00000000 table 4-6: advanced control registers 110 - 111 (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 65 KSZ8795clx the named indirect byte registers is a direct register which is used for pme/acl/eee indirect register access only. the indirect byte register 160 (0xa0) is used for read /write to all pme, eee, and acl indirect registers. register 117 (0x75): indirect data register 3 7 - 0 indirect data [31:24] bits[31:24] of indirect data r/w 00000000 register 118 (0x76): indirect data register 2 7 - 0 indirect data [23:6] bits[23:16] of indire ct data. r/w 00000000 register 119 (0x77): indirect data register 1 7 - 0 indirect data [15:8] bits[15:8] of indirect data. r/w 00000000 register 120 (0x78): indirect data register 0 7 - 0 indirect data [7:0] bits[7:0] of indirect data. r/w 00000000 table 4-8: advanced control registers 160, 124 - 127 address name description mode default register 160 (0xa0): indirect byte register (for pm e, eee, and acl registers) 7 - 0 indirect byte[7:0] byte data of indirect access. r/w 00000000 register 124 (0x7c): interrupt status register 7 - 5 reserved n/a dont change. ro 000 4p m e interrupt status 1 = pme interrupt request 0 = normal note: this bit reflects pme control registers, write to pme control register to clear this bit is set when pme is asserted. write a 1 to clear this bit (wc) ro 0 3 port 4 interrupt status 1 = port 4 interrupt request 0 = normal note: this bit is set by port 4 link change. write a 1 to clear this bit (wc) r/wc 0 2 port 3 interrupt status 1 = port 3 interrupt request 0 = normal note: this bit is set by a link change on port 3. write a 1 to clear this bit (wc) r/wc 0 1 port 2 interrupt status 1 = port 2 interrupt request 0 = normal note: this bit is set by a link change on port 2. write a 1 to clear this bit (wc) r/wc 0 0 port 1 interrupt status 1 = port 1 interrupt request 0 = normal note: this bit is set by link change on port 1. write a 1 to clear this bit (wc) r/wc 0 table 4-7: advanced control registers 112 - 120 (continued) address name description mode default downloaded from: http:///
KSZ8795clx ds00002112a-page 66 ? 2016 microchip technology inc. registers 128 and 129 can be used to map from 802.1p priority field 0 - 7 to the switchs four priority queues 0 - 3. 0x3 is the highest priority queues as priority 3 and 0x0 is the lowest priority queues as priority 0. register 125 (0x7d): interrupt mask register 7 - 5 reserved n/a dont change. ro 000 4p m e interrupt mask 1 = enable pme interrupt. 0 = normal r/w 0 3 port 4 interrupt mask 1 = enable port 4 interrupt. 0 = normal r/w 0 2 port 3 interrupt mask 1 = enable port 3 interrupt. 0 = normal r/w 0 1 port 2 interrupt mask 1 = enable port 2 interrupt. 0 = normal r/w 0 0 port 1 interrupt mask 1 = enable port 1 interrupt. 0 = normal r/w 0 register 126 (0x7e): acl interrupt status register 7 - 5 reserved n/a dont change. ro 000 4 - 0 acl_int_ status acl interrupt status, one bit per port 1 = acl interrupt detected. 0 = no acl interrupt detected. ro 00000 register 127 (0x7f): acl interrupt cont rol register 7 - 5 reserved n/a dont change. ro 000 4 - 0 acl_int_ enable acl interrupt enable, one bit per port 1 = acl interrupt enabled. 0 = acl interrupt disabled. r/w 00000 table 4-9: advanced control registers 128 - 129 address name description mode default register 128 (0x80): global control 12 7 - 6 tag_0x3 ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee 802.1p tag has a value of 0x3. r/w 0x1 5 - 4 tag_0x2 ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee 802.1p tag has a value of 0x2. r/w 0x1 3 - 2 tag_0x1 ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee 802.1p tag has a value of 0x1. r/w 0x0 1 - 0 tag_0x0 ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee 802.1p tag has a value of 0x0. r/w 0x0 register 129 (0x81): global control 13 7 - 6 tag_0x7 ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee 802.1p tag has a value of 0x7. r/w 0x3 table 4-8: advanced control regist ers 160, 124 - 127 (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 67 KSZ8795clx 5 - 4 tag_0x6 ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee 802.1p tag has a value of 0x6. r/w 0x3 3 - 2 tag_0x5 ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee 802.1p tag has a value of 0x5. r/w 0x2 1 - 0 tag_0x4 ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee 802.1p tag has a value of 0x4. r/w 0x2 table 4-10: advanced control registers 130 - 135 address name description mode default register 130 (0x82): global control 14 7 - 6 pri_2q[1:0] when the 2 queue s configuration is selected, these pri_2q[1:0] bits are used to map the 2-bit result of ieee 802.1p from register 128/129 or tos/diffserv from register 144-159 mapping (for 4 queues) into two queues low/high priorities. 2-bit result of ieee 802 .1p or tos/diffserv 00 (0) = map to low priority queue 01 (1) = prio_2q[0] map to low/high priority queue 10 (2) = prio_2q[1] map to low/high priority queue 11 (3) = map to high priority queue pri_2q[1:0]: 00 = result 0,1, 2 are low priority. 3 is high priority. 01 = not supported and should be avoided 10 = result 0,1 are low priority. 2, 3 are high priority (default). 11 = result 0 is low priority. 1, 2, 3 are high priority. r/w 10 5 - 0 reserved n/a dont change. ro 001000 register 131 (0x83): global control 15 7 - 6 reserved n/a dont change. ro 10 5 unknown unicast packet forward 1 = enable supporting unknown unicast packet for- ward 0 = disable r/w 0 4 - 0 unknown unicast packet forward port pap 00000 = filter unknown unicast packet 00001 = forward unknown unicast packet to port 1 00011 = forward unknown unicast packet to port 1, port 2 00111 = forward unknown unicast packet to port 1, port 2, and port 3 01111 = forward unknown unicast packet to port 1, port 2, port 3, and port 4 11111 = broadcast unknown unicast packet to all ports r/w 00000 register 132 (0x84): global control 16 7 - 6 reserved n/a dont change. ro 01 table 4-9: advanced control registers 128 - 129 (continued) address name description mode default downloaded from: http:///
KSZ8795clx ds00002112a-page 68 ? 2016 microchip technology inc. 5 unknown multicast packet forward (not including ip multicast packet) 1 = enable supporting unknown multicast packet forward 0 = disable r/w 0 4 -0 unknown multicast packet forward port map 00000 = filter unknown multicast packet 00001 = forward unknown multicast packet to port 1 00011 = forward unknown multicast packet to port 1, port 2 00111 = forward unknown multicast packet to port 1, port 2 and port 3 01111 = forward unknown multicast packet to port 1, port 2, port 3 and port 4 11111 = broadcast unknown multicast packet to all ports r/w 00000 register 133 (0x85): global control 17 7 - 6 reserved n/a dont change. ro 00 5 unknown vid packet forward 1 = enable supporting unknown vid packet for- ward 0 = disable r/w 0 4 - 0 unknown vid packet forward port map 00000 = filter unknown vid packet 00001 = forward unknown vid packet to port 1 00011 = forward unknown vid packet to port 1, port 2 00111 = forward unknown vid packet to port 1, port 2 and port 3 01111 = forward unknown vid packet to port 1, port 2, port 3 and port 4 11111 = broadcast unknown vid packet to all ports r/w 00000 register 134 (0x86): global control 18 7 reserved n/a dont change. ro 0 6 self-address filter enable 1 = enable filtering of self-address unicast and mul- ticast packet 0 = do not filter self-address packet note: the self-address filtering will filter packets on the egress port, self mac address is assigned in the register 104 - 109. r/w 0 5 unknown ip multicast packet forward 1 = enable supporting unknown ip multicast packet forward 0 = disable supporting unknown ip multicast packet forward r/w 0 table 4-10: advanced control registers 130 - 135 (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 69 KSZ8795clx the ipv4/ipv6 tos priority control registers implement a fu lly decoded 64-bit differentiated services code point (dscp) register used to determine priority from the 6-bit tos field in the ip header. the most significant 6 bits of the tos field are fully decoded into 64 possibilities, and the singular code that results is mapped to the value in the corresponding bit in the dscp register. 4 - 0 unknown ip multicast packet forward port map 00000 = filter unknown ip multicast packet 00001 = forward unknown ip multicast packet to port 1 00011 = forward unknown ip multicast packet to port 1, port 2 00111 = forward unknown ip multicast packet to port 1, port 2, and port 3 01111 = forward unknown ip multicast packet to port 1, port 2, port 3, and port 4 11111 = broadcast unknown ip multicast packet to all ports r/w 00000 register 135 (0x87): global control 19 7 - 6 reserved n/a dont change. ro 00 5 - 4 ingress rate limit period the unit period for calculating ingress rate limit: 00 = 16 ms 01 = 64 ms 1x = 256 ms r/w 01 3 queue- based egress rate limit enabled enable queue-based egress rate limit 0 = port-based egress rate limit (default) 1 = queue-based egress rate limit r/w 0 2 insertion source port pvid tag selection enable 1 = enable source port pvid tag insertion or non- insertion option on the egress port for each source port pvid-based on the ports control 8 registers. 0 = disable, all packets from any ingress port will be inserted pvid-based on port control 0 register bit[2]. r/w 0 1 - 0 reserved n/a dont change. ro 00 table 4-11: advanced control registers 144 - 159 address name description mode default register 144 (0x90): tos priority control register 0 7 - 6 dscp[7:6] ipv4 and ipv6 mapping the value in this field is used as the frames priority when bits [7:2] of the frames ip os/diffserv/traffic class value is 0x03. r/w 00 5 - 4 dscp[5:4] ipv4 and ipv6 mapping the value in this field is used as the frames priority when bits [7:2] of the frames ip os/diffserv/traffic class value is 0x02. r/w 00 3 - 2 dscp[3:2] ipv4 and ipv6 mapping the value in this field is used as the frames priority when bits [7:2] of the frames ip os/diffserv/traffic class value is 0x01. r/w 00 table 4-10: advanced control registers 130 - 135 (continued) address name description mode default downloaded from: http:///
KSZ8795clx ds00002112a-page 70 ? 2016 microchip technology inc. 1 - 0 dscp[1:0] ipv4 and ipv6 mapping the value in this field is used as the frames priority when bits [7:2] of the frames ip os/diffserv/traffic class value is 0x00. r/w 00 register 145 (0x91): tos priority control register 1 7 - 6 dscp[15:14] ipv4 and ipv6 mapping _ for value 0x07 r/w 00 5 - 4 dscp[13:12] ipv4 and ipv6 mapping _ for value 0x06 r/w 00 3 - 2 dscp[11:10] ipv4 and ipv6 mapping _ for value 0x05 r/w 00 1 - 0 dscp[9:8] ipv4 and ipv6 mapping _ for value 0x04 r/w 00 register 146 (0x92): tos priority control register 2 7 - 6 dscp[23:22] ipv4 and ipv6 mapping _ for value 0x0b r/w 00 5 - 4 dscp[21:20] ipv4 and ipv6 mapping _ for value 0x0a r/w 00 3 - 2 dscp[19:18] ipv4 and ipv6 mapping _ for value 0x09 r/w 00 1 - 0 dscp[17:16] ipv4 and ipv6 mapping _ for value 0x08 r/w 00 register 147 (0x93): tos priority control register 3 7 - 6 dscp[31:30] ipv4 and ipv6 mapping _ for value 0x0f r/w 00 5 - 4 dscp[29:28] ipv4 and ipv6 mapping _ for value 0x0e r/w 00 3 - 2 dscp[27:26] ipv4 and ipv6 mapping _ for value 0x0d r/w 00 1 - 0 dscp[25:24] ipv4 and ipv6 mapping _ for value 0x0c r/w 00 register 148 (0x94): tos priority control register 4 7 - 6 dscp[39:38] ipv4 and ipv6 mapping _ for value 0x13 r/w 00 5 - 4 dscp[37:36] ipv4 and ipv6 mapping _ for value 0x12 r/w 00 3 - 2 dscp[35:34] ipv4 and ipv6 mapping _ for value 0x11 r/w 00 1 - 0 dscp[33:32] ipv4 and ipv6 mapping _ for value 0x10 r/w 00 register 149 (0x95): tos priority control register 5 7 - 6 dscp[47:46] ipv4 and ipv6 mapping _ for value 0x17 r/w 00 5 - 4 dscp[45:44] ipv4 and ipv6 mapping _ for value 0x16 r/w 00 3 - 2 dscp[43:42] ipv4 and ipv6 mapping _ for value 0x15 r/w 00 1 - 0 dscp[41:40] ipv4 and ipv6 mapping _ for value 0x14 r/w 00 register 150 (0x96): tos priority control register 6 7 - 6 dscp[55:54] ipv4 and ipv6 mapping _ for value 0x1b r/w 00 5 - 4 dscp[53:52] ipv4 and ipv6 mapping _ for value 0x1a r/w 00 3 - 2 dscp[51:50] ipv4 and ipv6 mapping _ for value 0x19 r/w 00 1 - 0 dscp[49:48] ipv4 and ipv6 mapping _ for value 0x18 r/w 00 register 151 (0x97): tos priority control register 7 7 - 6 dscp[63:62] ipv4 and ipv6 mapping _ for value 0x1f r/w 00 5 - 4 dscp[61:60] ipv4 and ipv6 mapping _ for value 0x1e r/w 00 3 - 2 dscp[59:58] ipv4 and ipv6 mapping _ for value 0x1d r/w 00 1 - 0 dscp[57:56] ipv4 and ipv6 mapping _ for value 0x1c r/w 00 register 152 (0x98): tos priority control register 8 7 - 6 dscp[71:70] ipv4 and ipv6 mapping _ for value 0x23 r/w 00 5 - 4 dscp[69:68] ipv4 and ipv6 mapping _ for value 0x22 r/w 00 3 - 2 dscp[67:66] ipv4 and ipv6 mapping _ for value 0x21 r/w 00 1 - 0 dscp[65:64] ipv4 and ipv6 mapping _ for value 0x20 r/w 00 table 4-11: advanced control registers 144 - 159 (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 71 KSZ8795clx register 153 (0x99): tos priority control register 9 7 - 6 dscp[79:78] ipv4 and ipv6 mapping _ for value 0x27 r/w 00 5 - 4 dscp[77:76] ipv4 and ipv6 mapping _ for value 0x26 r/w 00 3 - 2 dscp[75:74] ipv4 and ipv6 mapping _ for value 0x25 r/w 00 1 - 0 dscp[73:72] ipv4 and ipv6 mapping _ for value 0x24 r/w 00 register 154 (0x9a): tos priority control register 10 7 - 6 dscp[87:86] ipv4 and ipv6 mapping _ for value 0x2b r/w 00 5 - 4 dscp[85:84] ipv4 and ipv6 mapping _ for value 0x2a r/w 00 3 - 2 dscp[83:82] ipv4 and ipv6 mapping _ for value 0x29 r/w 00 1 - 0 dscp[81:80] ipv4 and ipv6 mapping _ for value 0x28 r/w 00 register 155 (0x9b): tos pr iority control register 11 7 - 6 dscp[95:94] ipv4 and ipv6 mapping _ for value 0x2f r/w 00 5 - 4 dscp[93:92] ipv4 and ipv6 mapping _ for value 0x2e r/w 00 3 - 2 dscp[91:90] ipv4 and ipv6 mapping _ for value 0x2d r/w 00 1 - 0 dscp[89:88] ipv4 and ipv6 mapping _ for value 0x2c r/w 00 register 156 (0x9c): tos priority control register 12 7 - 6 dscp [103:102] ipv4 and ipv6 mapping _ for value 0x33 r/w 00 5 - 4 dscp [101:100] ipv4 and ipv6 mapping _ for value 0x32 r/w 00 3 - 2 dscp[99:98] ipv4 and ipv6 mapping _ for value 0x31 r/w 00 1 - 0 dscp[97:96] ipv4 and ipv6 mapping _ for value 0x30 r/w 00 register 157 (0x9d): tos priority control register 13 7 - 6 dscp [111:110] ipv4 and ipv6 mapping _ for value 0x37 r/w 00 5 - 4 dscp [109:108] ipv4 and ipv6 mapping _ for value 0x36 r/w 00 3 - 2 dscp [107:106] ipv4 and ipv6 mapping _ for value 0x35 r/w 00 1 - 0 dscp [105:104] ipv4 and ipv6 mapping _ for value 0x34 r/w 00 register 158 (0x9e): tos priority control register 14 7 - 6 dscp [119:118] ipv4 and ipv6 mapping _ for value 0x3b r/w 00 5 - 4 dscp [117:116] ipv4 and ipv6 mapping _ for value 0x3a r/w 00 3 - 2 dscp [115:114] ipv4 and ipv6 mapping _ for value 0x39 r/w 00 1 - 0 dscp [113:112] ipv4 and ipv6 mapping _ for value 0x38 r/w 00 register 159 (0x9f): tos priority control register 15 7 - 6 dscp [127:126] ipv4 and ipv6 mapping _ for value 0x3f r/w 00 5 - 4 dscp [125:124] ipv4 and ipv6 mapping _ for value 0x3e r/w 00 3 - 2 dscp [123:122] ipv4 and ipv6 mapping _ for value 0x3d r/w 00 table 4-11: advanced control registers 144 - 159 (continued) address name description mode default downloaded from: http:///
KSZ8795clx ds00002112a-page 72 ? 2016 microchip technology inc. 1 - 0 dscp [121:120] ipv4 and ipv6 mapping _ for value 0x3c r/w 00 table 4-12: advanced control registers 163 - 164 address name description mode default register 163 (0xa3): global control 20 7 reserved n/a dont change. ro 0 6 - 4 gmii/rgmi high-speed drive strength high-speed interfaces dr ive strength for gmii and rgmi 000 = 2 ma 001 = 4 ma 010 = 8 ma 011 = 12 ma 100 = 16 ma 101 = 20 ma 110 = 24 ma (default) 111 = 28 ma r/w 110 3 reserved n/a dont change. ro 0 2 - 0 mii/rmii low-speed drive strength low-speed interfaces drive strength for mii and rmii 000 = 2 ma 001 = 4 ma 010 = 8 ma (default) 011 = 12 ma 100 = 16 ma 101 = 20 ma 110 = 24 ma 111 = 28 ma r/w 010 register 164 (0xa4): global control 21 7 - 4 reserved n/a dont change. ro 0x2 3i p v 6 m l d snooping option ipv6 mld snooping option 1 = enable 0 = disable r/w 0 2i p v 6 m l d snooping enable ipv6 mld snooping enable 1 = enable 0 = disable r/w 0 1 - 0 reserved n/a dont change. ro 10 table 4-11: advanced control registers 144 - 159 (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 73 KSZ8795clx table 4-13: additional advanced control registers ( note 4-1 ) address name description mode default register 176 (0xb0): port 1 control 12 register 192 (0xc0): port 2 control 12 register 208 (0xd0): port 3 control 12 register 224 (0xe0): port 4 control 12 register 240 (0xf0): port 5 control 12 7 reserved ro 1 6 pass all frames port-based enable to pass all frames 1 = enable 0 = disable note: this is used in the port mirroring with rx sniff only. r/w 0 5 -4 reserved ro 00 3 insert source port pvid for untagged packet desti- nation to highest egress port register 176: insert source port 1 pvid for untagged frame at egress port 5 register 192: insert source port 2 pvid for untagged frame at egress port 5 register 208: insert source port 3 pvid for untagged frame at egress port 5 register 224: insert source port 4 pvid for untagged frame at egress port 5 register 240: insert source port 5 pvid for untagged frame at egress port 4 note: enabled by the register 135 bit[2]. r/w 0 2 insert source port pvid for untagged packet desti- nation to second highest egress port register 176: insert source port 1 pvid for untagged frame at egress port 4 register 192: insert source port 2 pvid for untagged frame at egress port 4 register 208: insert source port 3 pvid for untagged frame at egress port 4 register 224: insert source port 4 pvid for untagged frame at egress port 3 register 240: insert source port 5 pvid for untagged frame at egress port 3 note: enabled by the register 135 bit[2]. r/w 0 1 insert source port pvid for untagged packet desti- nation to second low- est egress port register 176: insert source port 1 pvid for untagged frame at egress port 3 register 192: insert source port 2 pvid for untagged frame at egress port 3 register 208: insert source port 3 pvid for untagged frame at egress port 2 register 224: insert source port 4 pvid for untagged frame at egress port 2 register 240: insert source port 5 pvid for untagged frame at egress port 2 note: enabled by the register 135 bit[2]. r/w 0 downloaded from: http:///
KSZ8795clx ds00002112a-page 74 ? 2016 microchip technology inc. 0 insert source port pvid for untagged packet desti- nation to lowest egress port register 176: insert source port 1 pvid for untagged frame at egress port 2 register 192: insert source port 2 pvid for untagged frame at egress port 1 register 208: insert source port 3 pvid for untagged frame at egress port 1 register 224: insert source port 4 pvid for untagged frame at egress port 1 register 240: insert source port 5 pvid for untagged frame at egress port 1 note: enabled by the register 135 bit[2]. r/w 0 register 177 (0xb1): port 1 control 13 register 193 (0xc1): port 2 control 13 register 209 (0xd1): port 3 control 13 register 225 (0xe1): port 4 control 13 register 241 (0xf1): port 5 control 13 7 - 2 reserved ro 000000 1 4 queue split enable this bit, in combination with register16/32/48/64/ 80 bit[0], will select the split of 1, 2, and 4 queues: {register 177 bit[1], register 16 bit[0] = }: 11 = reserved. 10 = the port output queue is split into four priority queues or if map 802.1p to priority 0-3 mode. 01 = the port output queue is split into two priority queues or if map 802.1p to priority 0-3 mode. 00 = single output queue on the port. there is no priority differentiation even though packets are classified into high and low priority. r/w 0 0 enable drop- ping tag 0 = disable tagged packets drop 1 = enable tagged packets drop r/w 0 register 178 (0xb2): port 1 control 14 register 194 (0xc2): port 2 control 14 register 210 (0xd2): port 3 control 14 register 226 (0xe2): port 4 control 14 register 242 (0xf2): port 5 control 14 7 enable port transmit queue 3 ratio 0 = strict priority, will transmit all the packets from this priority queue 3 before transmit lower priority queue. 1 = bits[6:0] reflect the packet number allow to transmit from this priority queue 3 within a certain time. r/w 1 6 - 0 port trans- mit queue 3 ratio[6:0] packet number for transmit queue 3 for highest priority packets in four queues mode. r/w 0001000 table 4-13: additional advanced control registers ( note 4-1 ) (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 75 KSZ8795clx register 179 (0xb3): port 1 control 15 register 195 (0xc3): port 2 control 15 register 211 (0xd3): port 3 control 15 register 227 (0xe3): port 4 control 15 register 243 (0xf3): port 5 control 15 7 enable port transmit queue 2 ratio 0 = strict priority, will transmit all the packets from this priority queue 2 before transmit lower priority queue. 1 = bits[6:0] reflect the packet number allow to transmit from this priority queue 1 within a certain time. r/w 1 6 - 0 port trans- mit queue 2 ratio[6:0] packet number for transmit queue 2 for high/low priority packets in high/low priority packets in four queues mode. r/w 0000100 register 180 (0xb4): port 1 control 16 register 196 (0xc4): port 2 control 16 register 212 (0xd4): port 3 control 16 register 228 (0xe4): port 4 control 16 register 244 (0xf4): port 5 control 16 7 enable port transmit queue 1 rate 0 = strict priority, will transmit all the packets from this priority queue 1 before transmit lower priority queue. 1 = bits[6:0] reflect the packet number allow to transmit from this priority queue 1 within a certain time. r/w 1 6 - 0 port trans- mit queue 1 ratio[6:0] packet number for transmit queue 1 for low-/high- priority packets in four queues mode and high-pri- ority packets in two queues mode. r/w 0000010 register 181 (0xb5): port 1 control 17 register 197 (0xc5): port 2 control 17 register 213 (0xd5): port 3 control 17 register 229 (0xe5): port 4 control 17 register 245 (0xf5): port 5 control 17 7 enable port transmit queue 0 rate 0 = strict priority, will transmit all the packets from this priority queue 0 before transmit lower priority queue. 1 = bits[6:0] reflect the packet number allow to transmit from this priority queue 0 within a certain time. r/w 1 6 - 0 port trans- mit queue 0 ratio[6:0] packet number for transmit queue 0 for lowest pri- ority packets in four queues mode and low priority packets in two queues mode. r/w 0000001 register 182 (0xb6): port 1 rate limit control register 198 (0xc6): port 2 rate limit control register 214 (0xd6): port 3 rate limit control register 230 (0xe6): port 4 rate limit control register 246 (0xf6): port 5 rate limit control 7 reserved ro 0 6 ingress limit port/priority based select 1 = ingress rate limit is port based 0 = ingress rate limit is priority based r/w 0 table 4-13: additional advanced control registers ( note 4-1 ) (continued) address name description mode default downloaded from: http:///
KSZ8795clx ds00002112a-page 76 ? 2016 microchip technology inc. 5 ingress limit bit/packets mode select 1 = rate limit is counted based on number of packet. 0 = rate limit is counted based on number of bit. r/w 0 4 ingress rate limit flow control enable 1 = flow control is asserted if the ports receive rate is exceeded. 0 = flow control is not asserted if the ports receive rate is exceeded. r/w 0 3 - 2 limit mode ingress limit mode these bits determine what type of frames are lim- ited and counted against ingress rate limiting. 00 = limit and count all frames. 01 = limit and count broadcast, multicast, and flooded unicast frames. 10 = limit and count broadcast and multicast frames only. 11 = limit and count broadcast frames only. r/w 00 1 count ifg count ifg bytes 1 = each frames minimum inter-frame gap. (ifg) bytes (12 per frame) are included in ingress and egress rate limiting calculations. 0 = ifg bytes are not counted. r/w 0 0 count pre count preamble bytes 1 = each frames preamble bytes (8 per frame) are included in ingress and egress rate limiting calcu- lations. 0 = preamble bytes are not counted. r/w 0 register 183 (0xb7): port 1 priority 0 ingress limit control 1 register 199 (0xc7): port 2 priority 0 ingress limit control 1 register 215 (0xd7): port 3 priority 0 ingress limit control 1 register 231 (0xe7): port 4 priority 0 ingress limit control 1 register 247 (0xf7): port 5 priority 0 ingress limit control 1 7 reserved ro 0 6 - 0 port based priority 0 ingress limit ingress data rate limit for priority 0 frames ingress traffic from this port is shaped according to the table 18 in rate limiting support sub-section. r/w 0000000 register 184 (0xb8): port 1 priority 1 ingress limit control 2 register 200 (0xc8): port 2 priority 1 ingress limit control 2 register 216 (0xd8): port 3 priority 1 ingress limit control 2 register 232 (0xe8): port 4 priority 1 ingress limit control 2 register 248 (0xf8): port 5 priority 1 ingress limit control 2 7 reserved ro 0 6 - 0 port-based priority 1 ingress limit ingress data rate limit for priority 1 frames ingress traffic from this port is shaped according to the table 18 in rate limiting support sub-section. r/w 0000000 register 185 (0xb9): port 1 priority 2 ingress limit control 3 register 201 (0xc9): port 2 priority 2 ingress limit control 3 register 217 (0xd9): port 3 priority 2 ingress limit control 3 register 233 (0xe9): port 4 priority 2 ingress limit control 3 register 249 (0xf9): port 5 priority 2 ingress limit control 3 7 reserved ro 0 table 4-13: additional advanced control registers ( note 4-1 ) (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 77 KSZ8795clx 6 - 0 port-based priority 2 ingress limit ingress data rate limit for priority 2 frames ingress traffic from this port is shaped according to the table 18 in rate limiting support sub-section. r/w 0000000 register 186 (0xba): port 1 priority 3 ingress limit control 4 register 202 (0xca): port 2 priority 3 ingress limit control 4 register 218 (0xda): port 3 priority 3 ingress limit control 4 register 234 (0xea): port 4 priority 3 ingress limit control 4 register 250 (0xfa): port 5 priority 3 ingress limit control 4 7 port-based ingress rate limit enable ingress data rate limit for priorities setting valid trigger port ingress rate limit engine to take effect for all the priority queues according to priority ingress limit control. note: any write to this register will trigger port ingress rate limit engine to take effect for all the pri- ority queues according to priority ingress limit con- trol. for the port priority 0 - 3 ingress rate limit control to take effect, bit[7] of in register 186, 202, 218, 234 and 250 for ports 1, 2, 3, 4 and 5, respec- tively will need to set last after configured bits[6:0] of port ingress limit control 1 - 4 registers. r/w 0 6 - 0 port-based priority 3 ingress limit ingress data rate limit for priority 3 frames ingress traffic from this port is shaped according to the table 18 in rate limiting support sub-section. r/w 0000000 register 187 (0xbb): port 1 queue 0 egress limit control 1 register 203 (0xcb): port 2 queue 0 egress limit control 1 register 219 (0xdb): port 3 queue 0 egress limit control 1 register 235 (0xeb): port 4 queue 0 egress limit control 1 register 251 (0xfb): port 5 queue 0 egress limit control 1 7 reserved ro 0 6 - 0 port queue 0 egress limit egress data rate limit for priority 0 frames egress traffic from this port is shaped according to the table 18 in rate limiting support sub-section. in four queues mode, it is lowest priority. in two queues mode, it is low priority. r/w 0000000 register 188 (0xbc): port 1 queue 1 egress limit control 2 register 204 (0xcc): port 2 queue 1 egress limit control 2 register 220 (0xdc): port 3 queue 1 egress limit control 2 register 236 (0xec): port 4 queue 1 egress limit control 2 register 252 (0xfc): port 5 queue 1 egress limit control 2 7 reserved ro 0 6 - 0 port queue 1 egress limit egress data rate limit for priority 1 frames egress traffic from this port is shaped according to the table 18 in rate limiting support sub-section. in four queues mode, it is low/high priority. in two queues mode, it is high priority. r/w 0000000 register 189 (0xbd): port 1 queue 2 egress limit control 3 register 205 (0xcd): port 2 queue 2 egress limit control 3 register 221 (0xdd): port 3 queue 2 egress limit control 3 register 237 (0xed): port 4 queue 2 egress limit control 3 register 253 (0xfd): port 5 queue 2 egress limit control 3 7 reserved ro 0 table 4-13: additional advanced control registers ( note 4-1 ) (continued) address name description mode default downloaded from: http:///
KSZ8795clx ds00002112a-page 78 ? 2016 microchip technology inc. note 4-1 in the port priority 0 - 3 ingress rate limit mode, it is necessary to set all related egress ports to two queues or four queues mode. in the port queue 0 - 3 egress rate limit mode, the highest priority get exact rate limit based on the rate select table, other priorities packets rate are based upon the ratio of the port control 14/15/16/ 17 registers when using more than one egress queue per port. 6 - 0 port queue 2 egress limit egress data rate limit for priority 2 frames egress traffic from this port is shaped according to the table 18 in rate limiting support sub-section. in four queues mode, it is high/low priority. r/w 0000000 register 190 (0xbe): port 1 queue 3 egress limit control 4 register 206 (0xce): port 2 queue 3 egress limit control 4 register 222 (0xde): port 3 queue 3 egress limit control 4 register 238 (0xee): port 4 queue 3 egress limit control 4 register 254 (0xfe): port 5 queue 3 egress limit control 4 7 reserved ro 0 6 - 0 port queue 3 egress limit egress data rate limit for priority 3 frames egress traffic from this port is shaped according to the table 18 in rate limiting support sub-section. in four queues mode, it is highest priority. r/w 0000000 table 4-14: advanced control registers 191 - 255 address name description mode default register 191 (0xbf): testing register 7 - 0 reserved n/a dont change. ro 0x80 register 207 (0xcf): reserved control register 7 - 0 reserved n/a dont change. ro 0x15 register 223 (0xdf): test register 2 7 - 0 reserved n/a dont change. ro 0x0c register 239 (0xef): test register 3 7 - 0 reserved n/a dont change. ro 0x32 register 255 (0xff): testing register 4 7 - 0 reserved n/a dont change. ro 0x00 table 4-15: indirect register descriptions control indirect address contents direct address 0x6e, function select bits[7-5] = 000, table_select bits[3-2] = 00 0x000 C 0x01f static mac address table entry 0 C 31 direct address 0x6e, function select bits[7-5] = 000, table_select bits[3-2] = 01 0x000 C 0x1ff vlan table bucket 0 C 1023 (4 entries per bucket) direct address 0x6e, function select bits[7-5] = 000, table_select bits[3-2] = 10 0x000 C 0x1ff dynamic mac address table entry 0 C 1023 table 4-13: additional advanced control registers ( note 4-1 ) (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 79 KSZ8795clx 4.4 static mac address table the KSZ8795clx incorporates a static and a dynamic address table. when a da look-up is requested, both tables will be searched to make a packet forwarding decision. when an sa look-up is requested, only the dynamic table is searched for aging, migration, and lear ning purposes. the static da look-up result will have precedence over the dynamic da look-up result. if there are da matches in both tabl es, the result from the static table will be used. the static table can only be accessed and controlled by an external spi ma ster (usually a processor). th e entries in the static table will not be aged out by KSZ8795clx. an external device does all addition, modification and deletion. note: register bit assignments are different for static mac table reads and static mac table write, as shown in the fol- lowing table. direct address 0x6e, function select bits[7-5] = 000, table_select bits[3-2] = 11 0x000 C 0x08f, 0x100 C 0x109 0x000 C 0x01f port 1 mib counters 0x020 C 0x03f port 2 mib counters 0x040 C 0x05f port 3 mib counters 0x060 C 0x07f port 4 mib counters 0x080 C 0x09f port 5 mib counters 0x100 C 0x113 total byte and dropped mib counter direct address 0x6e, function select bits[7-5] = 001, bits[3-0] = indirect address bits[11-8] = msb indirect address = port indirect register address 0xn {0xn, 6h00} C {0xn, 6h05} port-based 16-bit eee control registers 0 C 5 n C port number use indirect byte register (0xa0) direct address 0x6e, function select bits[7-5] = 010, bits[3-0] = indirect address bits[11-8] = msb indirect address = port indirect register address 0xn {0xn, 6h00} C {0xn, 6h1f} acl entry 0 C 15, 6h00 and 6h01 for entry 0, etc. n = port number use indirect byte register(0xa0) direct address 0x6e, function select bits[7-5] = 011, bits[3-0] = indirect address bits [11-8] = msb indirect address = port indirect register address 0xn {0xn, 8h00} C {0xn, 8h4ff} reserved for the factory. direct address 0x6e, function select bits[7-5] = 100, bits[3-0] = indirect address bits[11-8] = msb indirect address = port indirect register address 0xn {0xn, 8h00} C {0xn, 8h4ff} configuration registers, pme, etc. n = 0 - global n = 1 C 4 port number use indirect byte register(0xa0) direct address 0x6e, function select bits[7-5] = 101, bits[3-0] = indirect address bits [11-8] = msb indirect address = port indirect register address 0xn {0xn, 8h00} C {0xn, 8h4ff} reserved for the factory. table 4-16: static mac address table address name description mode default format of static mac table for reads (32 entries) 63 - 57 fid filter vlan id, repr esenting one of the 128 active vlans. ro 0000000 56 use fid 1 = use (fid+mac) to look-up in static table. 0 = use mac only to look-up in static table. ro 0 55 reserved ro 0 table 4-15: indirect register descriptions (continued) control indirect address contents downloaded from: http:///
KSZ8795clx ds00002112a-page 80 ? 2016 microchip technology inc. examples: 1. static address table read (read the 2nd entry) write to register 110 with 0x10 (read static table selected) write to register 111 with 0x1 (trigger the read operation) then read register 113 (63:56) read register 114 (55:48) read register 115 (47:40) read register 116 (39:32) 54 override 1 = override spanning tree transmit enable = 0 or receive enable = 0* setting. this bit is used for spanning tree implementation. 0 = no override. ro 0 53 valid 1 = this entry is valid, the look-up result will be used. 0 = this entry is not valid. ro 0 52 - 48 forwarding ports these 5 bits control the forward ports. for example: 00001 = forward to port 1 00010 = forward to port 2 00100 = forward to port 3 01000 = forward to port 4 10000 = forward to port 5 00110 = forward to port 2 and port 3 11111 = broadcasting (excluding the ingress port) ro 00000 47 - 0 mac address (da) 48-bit mac address. ro 0x0 format of static mac table for writes (32 entries) 62 - 56 fid filter vlan id, representing one of the 128 active vlans. w 0000000 55 use fid 1 = use (fid+mac) to look-up in static table. 0 = use mac only to look-up in static table. w0 54 override 1 = override spanning tree transmit enable = 0 or receive enable = 0 setting. this bit is used for spanning tree implementation. 0 = no override. w0 53 valid 1 = this entry is valid, the look-up result will be used. 0 = this entry is not valid. w0 52 - 48 forwarding ports these 5 bits control the forward ports. for example, 00001 = forward to port 1 00010 = forward to port 2 00100 = forward to port 3 01000 = forward to port 4 10000 = forward to port 5 00110 = forward to port 2 and port 3 11111 = broadcasting (excluding the ingress port) w 00000 47 - 0 mac address (da) 48-bit mac address. w 0 table 4-16: static mac address table (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 81 KSZ8795clx read register 117 (31:24) read register 118 (23:16) read register 119 (15:8) read register 120 (7:0) 2. static address table write (write the 8th entry) write register 113 (62:56) write register 114 (55:48) write register 115 (47:40) write register 116 (39:32) write register 117 (31:24) write register 118 (23:16) write register 119 (15:8) write register 120 (7:0) write to register 110 with 0x00 (write static table selected) write to register 111 with 0x7 (trigger the write operation) 4.5 vlan table the vlan table is used for vlan table look-up. if 802.1q vl an mode is enabled (register 5 bit[7] = 1), this table is used to retrieve vlan information that is associated with t he ingress packet. there are three fields for fid (filter id), valid, and vlan membership in the vlan table. the three fields must be initialized before the table is used. there is no vid field because 4096 vids are used as a dedicated memory address index into a 1024x52-bit memory space. each entry has four vlans. each vlan has 13 bits. four vlans need 52 bits. there are a total of 1024 entries to sup- port a total of 4096 vlan ids by using dedicated memory address and data bits. fid has 7 bits to support 128 active vlans. if 802.1q vlan mode is enabled, the KSZ8795clx assign s a vid to every ingress packet when the packet is untagged or tagged with a null vid, the packet is assigned with the default po rt vid of the ingress port. if the packet is tagged with non-null vid, the vid in the tag is used. the look-up process starts from the vlan table look-up based on vid number with its dedicated memory address and data bits. if the entry is not valid in the vlan table, the packet is dropped and no address learning occurs. if the entry is valid, the fid is retrieved. the fid+da and fid+sa lookups in mac tables are performed. the fid+da look-up determi nes the forwarding ports. if fid+da fa ils for look-up in the mac table, the packet is broadcast to all the members or specified member s (excluding the ingress port) based on the vlan table. if fid+sa fails, the fid+sa is learned. to communicate between different active vlans, set the same fid; otherwise set a different fid. table 4-17: vlan table address name description mode initial suggested value format of static vlan table (support max 4096 vlan id entries and 128 active vlans) 12 valid 1 = the entry is valid. 0 = entry is invalid. r/w 0 11 - 7 membership specifies which ports are members of the vlan. if a da look-up fails (no match in both static and dynamic tables), the packet associated with this vlan will be for- warded to ports specified in this field. e.g., 11001 means ports 5, 4, and 1 are in this vlan. r/w 111111 6 - 0 fid filter id. the KSZ8795clx supports 128 active vlans represented by these seven bit fields. fid is the mapped id. if 802.1q vlan is enabled, the look-up will be based on fid+da and fid+sa. r/w 0 downloaded from: http:///
KSZ8795clx ds00002112a-page 82 ? 2016 microchip technology inc. the vlan table configuration is organized as 1024 vlan sets , each vlan set consists of four vlan entries, to support up to 4096 vlan entries. each vlan set has total 60 bits and three reversed bits are inserted between entries. actually, 52 bits are used for the vlan set which should be read or written at the same time specif ied by the indirect address. the vlan entries in the vlan set are mapped to indirect data registers as follow: entry0[12:0] maps to the vl an set bits[12:0] {register 119[4:0], register 120[7:0]} entry1[12:0] maps to the vl an set bits[28:16] {register 117[4:0], regist er 118[7:0]} entry2[12:0] maps to the vl an set bits[44:32] {register 115[4:0], regist er 116[7:0]} entry3[12:0] maps to the vl an set bits[60:48] {register 113[4:0], regist er 114[7:0]} in order to read one vlan entry, the vlan set is read firs t and the specific vlan entry information can be extracted. to update any vlan entry, the vlan set is read first then only the desired vlan entry is updated and the whole vlan set is written back. the fid in the vlan table is 7 bits, so the vlan table supports unique 128 flow vlan groups. each vlan set address is 10 bits long (maximum is 1024) in the indirect address register 110 and 111, the bits[9:8] of vlan set address is at bits[1:0] of register 110, and the bits[7:0] of vlan set address is at bits [7:0] of register 111. each write and read can access up to four consecutive vlan entries. examples: 1. vlan table read (read the vid = 2 entry) write the indirect control and address registers first write to register 110 (0x6e) with 0x14 (read vlan table selected) write to register 111 (0x6f) with 0x0 (trigger the read operation for vid = 0, 1, 2, 3 entries) then read the indirect data regist ers bits[38:26] for vid = 2 entry read register 115 (0x73), (register 115 [4 :0] are bits[12:8] of vlan vid = 2 entry) read register 116 (0x74), (register 116 [7 :0] are bits[7:0] of vlan vid = 2 entry) 2. vlan table write (write the vid = 10 entry) read the vlan set that contains vid = 8, 9, 10, 11. write to register 110 (0x6e) with 0x14 (read vlan table selected) write to register 111 (0x6f) with 0x02 (trigger the re ad operation and vid = 8, 9, 10, 11 indirect address) read the vlan set first by the indirect data registers 113, 114, 115, 116, 117, 118, 119, 120. modify the indirect data registers bits[44:32] by the register 115 bit[4:0] and register 116 bits[7:0] as follows: write to register 115 (0x73), (register115 [4 :0] are bits[12:8} of vlan vid = 10 entry) write to register 116 (0x74), (register116 [7:0] are bits[7:0] of vlan vid = 10 entry) then write the indirect control and address registers write to register 110 (0x6e) with 0x04 (write vlan table selected) write to register 111 (0x6f) with 0x02 (trigger the wr ite operation and vid = 8, 9, 10, 11 indirect address) table 4-18 shows the relationship of the indire ct address/data registers and vlan id. table 4-18: vlan id and indirect registers indirect address high/low bit[9-0] for vlan sets indirect data registers bits for each vlan entry vid numbers vid bit[12-2] in vlan tag vid bit[1-0] in vlan tag 0b i t s [ 1 2 : 0 ]0 0 0 0 bits[28:16] 1 0 1 0 bits[44:32] 2 0 2 0 bits[60:48] 3 0 3 1b i t s [ 1 2 : 0 ]4 1 0 1 bits[28:16] 5 1 1 1 bits[44:32] 6 1 2 1 bits[60:48] 7 1 3 2b i t s [ 1 2 : 0 ]8 2 0 downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 83 KSZ8795clx 4.6 dynamic mac address table table 4-19 is read-only. examples: 1. dynamic mac address table read (read the 1s t entry), and retrieve the mac table size write to register 110 with 0x18 (read dynamic table selected) write to register 111 with 0x0 (trigger the read operation) and then read register 112 (71:64) read register 113 (63:56); // the above two registers show # of entries read register 114 (55:48) // if bit[55] is 1, restart (reread) from this register 2 bits[28:16] 9 2 1 2 bits[44:32] 10 2 2 2 bits[60:48] 11 2 3 :::::::::: ::::: 1023 bits[12:0] 4092 1023 0 1023 bits[28:16] 4093 1023 1 1023 bits[44:32] 4095 1023 2 1023 bits[60:48] 4095 1023 3 table 4-19: dynamic mac address table address name description mode default format of dynamic mac address table (1k entries) 71 mac empty 1 = there is no valid entry in the table. 0 = there are valid entries in the table. ro 1 70 - 61 no. of valid entries indicates how many valid entries in the table. 0x3ff means 1k entries 0x1 and bit[71] = 0: means 2 entries 0x0 and bit[71]= 0: means 1 entry 0x0 and bit[71] = 1: means 0 entry ro 0 60 - 59 time stamp 2-bit counters for internal aging ro 58 - 56 source port the source port where fid+mac is learned. 000 = port 1 001 = port 2 010 = port 3 011 = port 4 100 = port 5 ro 0x0 55 data ready 1 = the entry is not ready, retry until this bit is set to 0. 0 = the entry is ready. ro 54 - 48 fid filter id ro 0x0 47 - 0 mac address 48-bit mac address ro 0x0 table 4-18: vlan id and indirect registers (continued) indirect address high/low bit[9-0] for vlan sets indirect data registers bits for each vlan entry vid numbers vid bit[12-2] in vlan tag vid bit[1-0] in vlan tag downloaded from: http:///
KSZ8795clx ds00002112a-page 84 ? 2016 microchip technology inc. read register 115 (47:40) read register 116 (39:32) read register 117 (31:24) read register 118 (23:16) read register 119 (15:8) read register 120 (7:0) 2. dynamic mac address table read (read the 257th entry), without retrieving number of entries information write to register 110 with 0x19 (read dynamic table selected) write to register 111 with 0x1 (trigger the read operation) and then read register 112 (71:64) read register 113 (63:56) read register 114 (55:48) // if bit[55] is 1, restart (reread) from this register read register 115 (47:40) read register 116 (39:32) read register 117 (31:24) read register 118 (23:16) read register 119 (15:8) read register 120 (7:0) 4.7 pme indirect registers the pme registers are provided on a global and per-port bas is. these registers are read/w rite using indirect memory access, as shown in table 4-20 . table 4-20: pme indirect registers address name description mode default global pme control register reg. 110 (0x6e) bits[7:5] =100 for pme, reg.110 bi ts[3:0] = 0x0 for the indirect global register, reg. 111 (0x6f) bits[7:0] = offset to access the indirect byte register 0xa0. offset: 0x00 (bits[31:24]), 0x01 (bits[23:16]), 0x02 (bit[15:8]), 0x03 (bits[7:0]). location: (100 pme) -> {0x0, offset} -> 0xa0 holds the data. 31 - 2 reserved ro all 0 1 pme output enable 1= pme output pin is enabled. 0= pme output pin is disabled. r/w 0 0 pme output polarity 1= pme output pin is active-high. 0= pme output pin is active-low. r/w 0 port pme control status register reg. 110 (0x6e) bits[7:5] =100 for pme, reg. 110 bits[3:0 ] = 0xn for the indirect port register (n = 1,2,3,4). reg. 111 (0x6f) bits[7:0] = offset to access the indirect byte register 0xa0. offset: 0x00 (bits[31: 24]), 0x01 (bits [23:16]), 0x02 (bits[5:8]), 0x03 (bits[7:0]). location: (100 pme) -> {0xn, of fset} -> 0xa0 holds the data. 31 - 3 reserved ro all 0 2 magic packet detect 1 = magic packet is detected at any port (write 1 to clear). 0 = no magic packet is detected. r/w w1c 0 1 link-up detect 1 = link up is detected at any port (write 1 to clear). 0 = no link-up is detected. r/w w1c 0 0e n e r g y detect 1 = energy is detected at any port (write 1 to clear). 0 = no energy is detected. r/w w1c 0 downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 85 KSZ8795clx programming examples read operation 1. use the indirect access control register to select re gister to be read, to read global pme control register. write 0x90 to the register 110 (0x6e) // pme selected and read operation, and 4 msbs of port number (register 110 bits[3:0]) = 0 for the global pme register. 2. write 0x03 to the register 111 (0x6f) // trigger the read operation for bits [7:0] of the global pme control register. 3. read the indirect byte register 160 (0xa0) // get the value of the global pme control register. write operation 1. write 0x80 to the register 110 (0x6 e) //pme selected and writ e operation, and 4 msbs of port number = 0 for the global pme register. 2. write 0x03 to the register 111 (0x6f) // select write the bits [7:0] of the global pme control address register. 3. write new value to the indirect byte register 160 bits [7:0] (0xa0) //write value to the global pme control reg- ister of the indirect pme data register by t he assigned the indirect data register address. port pme control mask register reg. 110 (0x6e) bits[7:5]=100 fo r pme, reg. 110 bits[3:0] = 0xn for port (n = 1, 2, 3, 4). reg. 111 (0x6f) bits[7:0]= offset to access the indirect byte register 0xa0. offset: 0x04 (bits[31:24]), 0x05 (bits[23:16]), 0x06 (bits[15:8]), 0x07 (bits[7:0]). location: (100 pme) -> {0xn, offset} -> 0xa0 holds the data. 31 - 3 reserved ro all 0 2 magic packet detect enable 1 = the pme pin will be asserted when a magic packet is detected at host qmu. 0 = the pme pin will not be asserted by the magic packet detection. r/w 0 1 link-up detect enable 1 = the pme pin will be asserted when a link-up is detected at any port. 0 = the pme pin will not be asserted by the link-up detection. r/w 0 0e n e r g y detect enable 1 = the pme pin will be asserted when energy on line is detected at any port. 0 = the pme pin will not be asserted by the energy detection. r/w 0 table 4-20: pme indirect registers (continued) address name description mode default downloaded from: http:///
KSZ8795clx ds00002112a-page 86 ? 2016 microchip technology inc. 4.8 acl rule table and acl indirect registers 4.8.1 acl register and programming model the acl registers are accessible by the mi crocontroller through a serial interface. the per-port register set is accessed through indirect addressing mechanism. the acl entries are stored in the format shown in the following figure. each acl rule list table can input up to 16 entries per port, with a total of five acl rule list tables that can be set for five por ts. to update any port-based acl r egisters, it is suggested to execute a read modify write sequence for each 128-bit (112 are used) entry addressed by the indirect address register to ensure the integrity of control content. minimum two indi- rect control writes and two indirect control reads are n eeded for each acl entry read access (indirect data read shall follow), and minimum one indirect control read and three indi rect control writes are requ ired for each acl entry write access. each 112-bit port-based acl word entry (acl wo rd) is accomplished through a sequence of the indirect access control 0 registers 110 (0x6e) a ccesses by specifying the bits[3:0] 4-bit port number (indirect address [11:8]) and 8-bit indirect register address (indirect address[7:0]) in the indirect access contro l 1 register 111 (0x6f). the address numbers 0x00-0x0d are used to specify the byte locati on of each entry (see above figure), address 0x00 indi- cates the byte 15 (msb) of each 128-bit entry, address 0x01 indicates the byte 14 etc., bytes at address 0x0e and 0x0f are reserved for the future. address 0x10 and 0x11 hold bi t-wise byte enable for each entry. address 0x12 is used as control and status register. the format of these registers is defined in the acl indirect registers sub-section. 4.8.2 acl indirect registers table 4-21 is used to implement acl mode selection and filtering on a per-port basis. figure 4-2: acl table access downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 87 KSZ8795clx table 4-21: acl indirect regi sters for 14 byte acl rules address name description mode default port_acl_0 acl port register 0 (0x00) reg. 110 (0x6e) bits[7:5] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x00 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. processing field 7 - 4 reserved ro 0x0 3 - 0 frn[3:0] first rule number this is for the first rule number of the rule set. there are total 16 entries per port in acl rule table. each single rule can be set with other rule for a rule set by the acl port register 12 (0x0c) and regis- ter 13 (0x0d). regardless single rule or rule set, have to assign an entry for using which action field by frn[3:0]. r/w 0000 port_acl_1 acl port register 1 (0x01) reg. 110 (0x6e) bits[7:5] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x01 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. matching fields 7 - 6 reserved ro 00 5 - 4 md[1:0] mode 00 = disable the current rule list, no action taken 01 = qualify rules for layer 2 mac header filtering 10 = is used for layer 3 ip address filtering 11 = performs layer 4 tcp port number/protocol filtering r/w 00 downloaded from: http:///
KSZ8795clx ds00002112a-page 88 ? 2016 microchip technology inc. 3 - 2 enb[1:0] enable when md=01: 00 = the 11 bits from pm, p, rep, mm in action field specify a count value for packets matching mac address and type in matching field. the count unit is defined in forward field bit[4]; bit[4] = 0, s will be used. bit[4] = 1, ms will apply. the forwarded field bit[3] determines the algo- rithm used to generate interrupt when counter ter- minated. bit[3] = 0, an 11-bit counter will be loaded with the count value from the list and start counting down every unit time. an interrupt will be generated when expires, i.e., next qualified packet has not been received within the period specified by the value. bit[3] = 1, the counter is incremented every matched packet received and the interrupt is gen- erated while terminal count reached, the count resets thereafter. 01 = mac address bit field is participating in test. 10 = mac type bit field is used for test. 11 = both mac address and type are tested against these bit fields in the list. when md=10: 00 = reserved. 01 = ip address and mask or ip protocol is enabled to be tested accordingly. 10 = sa and da are compared; the drop/forward decision is based on the e/q bit setting. 11 = reserved when md=11: 00 = protocol comparison is enabled. 01 = tcp/udp address comparison is selected. 10 = it is same with 01 11 = the sequence number of tcp is compared. r/w 00 1 s_d source/destination address 0 = da is used to compare. 1 = sa is used to compare r/w 0 0 eq compare equal 0 = match if they are not equal. 1 = match if they are equal. r/w 0 port_acl_2 acl port register 2 (0x02) reg. 110 (0x6e) bits[7:5 ] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x02 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. matching fields for layer 2 7 - 0 mac_addr [47:40] mac address r/w 00000000 table 4-21: acl indirect register s for 14 byte acl rules (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 89 KSZ8795clx port_acl_3 acl port register 3 (0x03) reg. 110 (0x6e) bits[7:5] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x03 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. matching fields for layer 2 7 - 0 mac_addr [39:32] mac address r/w 00000000 port_acl_4 acl port register 4 (0x04) reg. 110 (0x6e) bits[7:5] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x04 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. matching fields for layer 2 7 - 0 mac_addr [31:24] mac address r/w 00000000 port_acl_5 acl port register 5 (0x05) reg. 110 (0x6e) bits[7:5] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x05 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. matching fields for layer 2 7 - 0 mac_addr [23:16] mac address r/w 00000000 port_acl_6 acl port register 6 (0x06) reg. 110 (0x6e) bits[7:5] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x06 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. matching fields for layer 2 7 - 0 mac_addr [15:8] mac address r/w 00000000 port_acl_7 acl port register 7 (0x07) reg. 110 (0x6e) bits[7:5] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x07 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. matching fields for layer 2 7 - 0 mac_addr [7:0] mac address r/w 00000000 port_acl_8 acl port register 8 (0x08) reg. 110 (0x6e) bits[7:5] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x08 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. matching fields for layer 2 7 - 0 type[15:8] ether type r/w 00000000 table 4-21: acl indirect register s for 14 byte acl rules (continued) address name description mode default downloaded from: http:///
KSZ8795clx ds00002112a-page 90 ? 2016 microchip technology inc. port_acl_9 acl port register 9 (0x09) reg. 110 (0x6e) bits[7:5 ] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x09 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. matching fields for layer 2 7 - 0 type[7:0] ether type r/w 00000000 note: layer 2, layer 3, and layer 4 in matching field should be in different entries. same layer should be in same entry. port_acl_2 acl port register 2 (0x02) reg. 110 (0x6e) bits[7:5 ] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x02 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. matching fields for layer 3 7 - 0 ip_addr [31:24] ip address r/w 00000000 port_acl_3 acl port register 3 (0x03) reg. 110 (0x6e) bits[7:5 ] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x03 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. matching fields for layer 3 7 - 0 ip_addr [23:16] ip address r/w 00000000 port_acl_4 acl port register 4 (0x04) reg. 110 (0x6e) bits[7:5 ] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x04 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. matching fields for layer 3 ip 7 - 0 ip_addr [15:8] ip address r/w 00000000 port_acl_5 acl port register 5 (0x05) reg. 110 (0x6e) bits[7:5] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x05 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. matching fields for layer 3 7 - 0 ip_addr [7:0] ip address r/w 00000000 port_acl_6 acl port register 6 (0x06) reg. 110 (0x6e) bits[7:5 ] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x06 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. matching fields for layer 3 7 - 0 ip_mask [31:24] ip mask r/w 00000000 table 4-21: acl indirect register s for 14 byte acl rules (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 91 KSZ8795clx port_acl_7 acl port register 7 (0x07) reg. 110 (0x6e) bits[7:5] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x07 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. matching fields for layer 3 7 - 0 ip_mask [23:16] ip mask r/w 00000000 port_acl_8 acl port register 8 (0x08) reg. 110 (0x6e) bits[7:5] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x08 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. matching fields for layer 3 7 - 0 ip_mask [15:8] ip mask r/w 00000000 port_acl_9 acl port register 9 (0x09) reg. 110 (0x6e) bits[7:5] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x09 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. matching fields for layer 3 7 - 0 ip_mask [7:0] ip mask r/w 00000000 note: layer 2, layer 3, and layer 4 in matching field should be in different entries. same layer should be in same entry. port_acl_2 acl port register 2 (0x02) reg. 110 (0x6e) bits[7:5] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x02 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. matching fields for layer 4 7 - 0 max port [15:8] for range of tcp port number or sequence num- ber matching r/w 00000000 port_acl_3 acl port register 3 (0x03) reg. 110 (0x6e) bits[7:5] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x03 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. matching fields for layer 4 7 - 0 min port [7:0] for range of tcp port number or sequence num- ber matching r/w 00000000 port_acl_4 acl port register 4 (0x04) reg. 110 (0x6e) bits[7:5] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x04 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. matching fields for layer 4 7 - 3 reserved ro 00000 table 4-21: acl indirect register s for 14 byte acl rules (continued) address name description mode default downloaded from: http:///
KSZ8795clx ds00002112a-page 92 ? 2016 microchip technology inc. 2 - 1 pc[1:0] 00 = the port comparison is disabled. 01 = matching either one of max or min. 10 = match if the port number is in the range of max and min. 11 = match if the port nu mber is out of the range r/w 00 0 pro[7] ip protocol for the ip protocol to be matched 0 port_acl_5 acl port register 5 (0x05) reg. 110 (0x6e) bits[7:5 ] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x05 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. matching fields for layer 4 7 - 1 pro[6:0] ip protocol for the ip protocol to be matched r/w 0000000 0 fme flag match enable 0 = disable tcp flag matching 1 = enable tcp flag matching r/w 0 port_acl_6 acl port register 6 (0x06) reg. 110 (0x6e) bits[7:5 ] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x06 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. matching fields for layer 4 7 - 0 fmsk[7:0] tcp flag mask r/w 00000000 port_acl_7 acl port register 7 (0x07) reg. 110 (0x6e) bits[7:5 ] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x07 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. matching fields for layer 4 7 - 0 flag[7:0] tcp flag r/w 00000000 port_acl_8 acl port register 8 (0x08) reg. 110 (0x6e) bits[7:5 ] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x08 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. 7 - 0 reserved ro 00000000 port_acl_9 acl port register 9 (0x09) reg. 110 (0x6e) bits[7:5 ] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x09 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. 7 - 0 reserved ro 00000000 note: layer 2, layer 3, and layer 4 in matching field should be in different entries. same layer should be in same entry. table 4-21: acl indirect register s for 14 byte acl rules (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 93 KSZ8795clx port_acl_a acl port register 10 (0x0a) reg. 110 (0x6e) bits[7:5] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x0a to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. action field 7 - 6 pm[1:0] priority mode 00 = no priority is selected; the priority determined by qos/classification is used in the tagged packets. 01 = priority in p [2:0] bits field is used if it is greater than qos re sult in the 3-bit priority field of the tagged packets received. 10 = priority in p [2:0] bits field is used if it is smaller than qos result in the 3-bit priority field of the tagged packets received. 11 = p [2:0] bits field will replace the 3-bit priority field of the tagged packets received. r/w 00 5 - 3 p[2:0] priority note: the 3-bit priority value to be used depends on pm [1:0] setting in bits[7:6]. r/w 000 2 rpe remark priority enable 0 = no remarking is necessary. 1 = vlan priority bits in the packets are replaced by rp[2:1] bits fiel d below in the list. r/w 0 1 - 0 rp[2:1] remark priority 00 = priority 0 01 = priority 1 10 = priority 2 11 = priority 3 r/w 00 port_acl_b acl port register 11 (0x0b) reg. 110 (0x6e) bits[7:5] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x0b to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. action field 7 rp[0] remark priority r/w 0 6 - 5 mm[1:0] map mode 00 = no forwarding remapping is necessary. dont use the forwarding map in forward field; use the forwarding map from the look-up table only. 01 = the forwarding map in forward field is ored with the forwarding map from the look-up table. 10 = the forwarding map in forward field is anded with the forwarding map from the look-up table. 11 = the forwarding map in forward field replaces the forwarding map from the look-up table. r/w 00 table 4-21: acl indirect register s for 14 byte acl rules (continued) address name description mode default downloaded from: http:///
KSZ8795clx ds00002112a-page 94 ? 2016 microchip technology inc. 4 - 0 forward [4:0] port map each bit indicates forwarding decision of one port. bit[0] = port 1 bit[1] = port 2 bit[2] = port 3 bit[3] = port 4 bit[4] = port 5 when md = 01 and enb = 00, bit[4] is used as count unit: 0 = s 1 = ms bit[3] is used to select count modes: 0 = count down in the 11-bit counter from an assigned value in the action field pm, p, rpe, rp, and mm, an interrupt will be generated when expired. 1 = count up in the 11-bit counter for every matched packet received up to reach an assigned value in the action field pm, p, rpe, rp and mm, and then an interrupt will be generated. note: see enb field description for detail. r/w port_acl_c acl port register 12 (0x0c) reg. 110 (0x6e) bits[7:5 ] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x0c to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. processing field 7 - 0 ruleset [15:8] rule set each bit indicates this entry in bits 0 to 16, total 16 entries of the rule list can be assigned for the rule set to be used in the rules cascade per port. r/w 00000000 port_acl_d acl port register 13 (0x0d) reg. 110 (0x6e) bits[7:5 ] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x0d to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. processing field 7 - 0 ruleset [7:0] rule set each bit indicates this entry in bits 0 to 16, total 16 entries of the rule list can be assigned for the rule set to be used in the rules cascade per port. r/w 00000000 table 4-22: temporal storage for 14 bytes acl rules address name description mode default port_acl_byte_enb_msb acl port register 14 (0x10) reg. 110 (0x6e) bits[7:5 ] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, and 4. reg. 111 (0x6f) bits[7:0] = offset 0x10 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. 7 - 6 reserved ro 00 table 4-21: acl indirect register s for 14 byte acl rules (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 95 KSZ8795clx 5 - 0 byte_enb [13:8] byte enable in acl table; 14-byte per entry 1 = byte is selected for read/write 0 = byte is not selected bit[0] of byte_enb[13:0] is for byte address 0x0d in acl table entry, bit[1] of byte_enb[13:0] is for byte address 0x0c in acl table entry, etc. bit[13] of byte_enb[13:0] is for byte address 0x00 in acl table entry. r/w 0 port_acl_ byte_enb_lsb acl port register 15 (0x11) reg. 110 (0x6e) bits[7:5] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x11 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. 7 - 0 byte_enb [7:0] byte enable in acl table; 14-byte per entry 1 = byte is selected for read/write 0 = byte is not selected bit[0] of byte_enb[13:0] is for byte address 0x0d in acl table entry, bit[1] of byte_enb[13:0] is for byte address 0x0c in acl table entry, etc. bit[13] of byte_enb[13:0] is for byte address 0x00 in acl table entry. r/w 0x00 table 4-23: acl read/write control address name description mode default port_acl_access_control1 acl port register 16 (0x12) reg. 110 (0x6e) bits[7:5] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x12 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. 7 reserved ro 0 6w r i t e _ status write operation status 1 = write completed 0 = write is in progress ro 1 5 read_ status read operation status 1 = read completed 0 = read is in progress ro 1 4w r i t e _ read request type 1 = write 0 = read r/w 0 table 4-22: temporal storage for 14 bytes acl rules (continued) address name description mode default downloaded from: http:///
KSZ8795clx ds00002112a-page 96 ? 2016 microchip technology inc. the acl registers can be programmed us ing the read/write examples following: examples: read operation 1. steps to set byte enable register to select all bytes in acl word from 0x00-0x0d in acl table entry: use the indirect access control register to select register to be read. to read entry0 that is 1st entry of port 1: write 0x41 to register 110 (0x6e) // select acl and write to port 1 (port 2, 3, 4, an d 5 are 0x42, 0x43, 0x44, and 0x45) write 0x10 to register 111 (0x6f) // trigger the write oper ation for port 1 in the acl port register 14 (byte enable msb register) address. write 0x3f into the indirect byte register 160 (0xa0) for msb of byte enable word. write 0x41 to register 110 (0x6e) // select write to port 1. write 0x11 to register 111 (0x6f) // trigger the write operation for port 1 in the acl port register 15 (byte enable lsb register) address. (the above 2 may be part of burst). write 0xff into the indirect byte register 160 (0xa0) for lsb of byte enable word. write 0x41 to register 110 (0x6e) // se lect acl and write operations to port 1. write 0x12 to register 111 (0x6f) // write acl read/write control register address 0x12 to the indirect address in register 111 to trigger the read operation for port 1 in th e acl port register 16 (acl access control register) to read entry 0. write 0x00 into the indirect byte register 160 (0xa0)//acl port register 16 (0x12) bit[4] = 0 to read acl and bits[3:0] = 0x0 for entry 0. 2. steps set acl control register to read acl entry word 0). write 0x51 to register 110 (0x6e) //select acl and read to port 1 (port 2, 3, 4, an d 5 are 0x52, 0x53, 0x54 and 0x55). write 0x12 to register 111 (0x6f) //trigger the read operat ion for port 1 in the acl port register 16 (acl access control 1). read the indirect byte register 160 (0xa0) to get data (i f bit[5] is set, the read completes in the acl port register 16 [0x12] and goes to next step. ot herwise, repeat the above polling step). write 0x51 to register 110 (0x6e) // select read to port 1. 3 - 0 acl_entry _address acl entry address 0000 = entry 0. 0001 = entry 1. .. 1111 = entry 15. r/w 0000 port_acl_ access_control2 acl port register 17 (0x13) reg. 110 (0x6e) bits[7:5 ] = 010 for acl, reg. 110 bits[3:0] = 0xn for ports 1, 2, 3, 4, and 5. reg. 111 (0x6f) bits[7:0] = offset 0x13 to access the indirect byte register 0xa0. location: (010 acl) -> {0xn, offset} -> 0xa0 holds the data. 7 - 1 reserved ro 0000000 0f o r c e d l r miss 1 = dlr filtering uses single acl entry. dlr packet matching the acl entry will be considered as miss 0 = dlr filtering uses multiple acl entries. dlr packet matching the rule set for dlr packet will be considered as hit. note: dlr is defined as device level redun- dancy. r/w 0 table 4-23: acl read/write control (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 97 KSZ8795clx write 0x00 to register 111 (0x6f) // trigger the read/burst read operation(s) based on the byte enable register set- ting by the port 1 acl access register 0 (0x00). read/burst read the indirect byte register 160 (0xa0) // to get data of acl entry word 0, write 0x00 to 0x0d indirect address and read register 160 (0xa0) after each byte address write to register 111 (0x6f). write operation 1. steps set byte enable register to select odd address bytes in acl word: use the indirect access control register to select register to be written. to writ e even byte number of 15th entry of port 5: write 0x55 to register 110 (0x6e) // select acl and read to port 5. write 0x12 to register 111 (0x6f) // trigger the read operation for port 5 acl access control register read. read the indirect byte register 160 (0xa0) to get data (i f bit[6] is set, the previous write completes and go to next step. otherwise, repeat the above polling step). write 0x45 to register 110 (0x6e) // select acl and write to port 5. write 0x00 to register 111 (0x6f) //set offs et address for port 5 acl port register 0. write/burst write the indirect byte regi ster 160 (0xa0) for acl port register 0, 1, 2, ,13 from 0x00 to 0x0d) (write or burst write even bytes of port 5 acl access registers 0, 1, , 13 to holding buffer). write 0x45 to register 110 (0x6e) // select acl and write to port 5. write 0x10 to register 111 (0x6f) // trigger the write oper ation for port 5 in the acl port register 14 (byte enable msb register). write 0x15 into the indirect byte register 160 (0xa0) fo r msb of byte enable word to enable odd bytes address 0x01, 0x03 and 0x05. 2. steps set acl control register to writ e acl entry word 15 from holding buffer: write 0x45 to register 110 (0x6e) // select write to port 5. write 0x11 to register 111 (0x6f) // trigger the write operation for port 5 in the acl port register 15 (byte enable lsb register). write 0x55 into the indirect byte register 160 (0xa0) for lsb of byte enable word to enable odd bytes address 0x07, 0x09, 0x0b and 0x0d. write 0x45 to register 110 (0x6e) // select write to port 5. write 0x12 to register 111 (0x6f) // write the port acl access control register address (0x12) to the indirect address register 111 for setting the write operation to port 5 in the acl port register 16 to write entry 15 bytes 1, 3, 5,13. write 0x1f into the indirect byte register 160 (0xa0) // for the write operation to 15th entry in the acl port register 16 (0x12) bit4=1 to write acl, bi ts[3:0] = 0xf to write entry 15. the bit arrangement of the example above assumes layer 2 rule of mode = 01 in acl port register 1 (0x01), refer to acl format for mode = 10 and 11. 4.9 eee indirect registers the eee function is for all copper por ts only. the eee registers are provided on global and per-por t basis. these reg- isters are read/write using indirect memory access as below: lpi means low power idle. table 4-24: eee global registers address name description mode default eee global register 0 global eee qm buffer control register reg. 110 (0x6e) bits[7:5 ] = 001 for eee, reg. 110 bits[3:0] = 0 x0 for the indirect global register, reg. 111 (0x6f) bits[7:0] = offset to access the indirect byte register 0xa0. offset: 0x30 (bits[15:8]), 0x31 (bits[7:0]) location: (001 eee) -> {0x0, off set} -> 0xa0 holds the data. 15 - 8 reserved ro 0x40 downloaded from: http:///
KSZ8795clx ds00002112a-page 98 ? 2016 microchip technology inc. 7l p i terminated by input traf- fic enable 1 = lpi request will be stopped if input traffic is detected. 0 = lpi request wont be stopped by input traffic. r/w 0 6 - 0 reserved ro 0x10 eee global register 1 global empty txq to lpi wait time control register reg. 110 (0x6e) bits[7:5 ] = 001 for eee, reg. 110 bits[3:0] = 0 x0 for the indirect global register, reg. 111 (0x6f) bits[7:0] = offset to access the indirect byte register 0xa0. offset: 0x32 (bits[15:8]), 0x33 (bits[7:0]) location: (001 eee) -> {0x0, off set} -> 0xa0 holds the data. 15 - 0 empty txq to lpi wait time this register specifies the time that the lpi request will be generated after a txq has been empty exceeds this configured time. this is only valid when eee 100bt is enabled. this setting will apply to all the ports. the unit is 1.3 ms. the default value is 1.3s (range from 1.3 ms to 86 seconds) r/w 0x10 eee global register 2 global eee pcs di agnostic register reg. 110 (0x6e) bits[7:5 ] = 001 for eee, reg. 110 bits[3:0] = 0 x0 for the indirect global register, reg. 111 (0x6f) bits[7:0] = offset to access the indirect byte register 0xa0. offset: 0x34(bits[15:8]), 0x35 (bits[7:0]) location: (001 eee) -> {0x0, off set} -> 0xa0 holds the data. 15 - 12 reserved ro 0x6 11 - 8 reserved ro 0x8 7 - 4 reserved ro 0x0 3 port 4 next page enable 1 = enable next page exchange during auto-nego- tiation. 0 = skip next page exchange during auto-negotia- tion. r/w 1 2 port 3 next page enable 1 = enable next page exchange during auto-nego- tiation. 0 = skip next page exchange during auto-negotia- tion. r/w 1 1 port 2 next page enable 1 = enable next page exchange during auto-nego- tiation. 0 = skip next page exchange during auto-negotia- tion. r/w 1 0 port 1 next page enable 1 = enable next page exchange during auto-nego- tiation. 0 = skip next page exchange during auto-negotia- tion. r/w 1 eee global register 3 global eee minimum lpi cycles before back to idle control register reg. 110 (0x6e) bits[7:5 ] = 001 for eee, reg. 110 bits[3:0] = 0 x0 for the indirect global register, reg. 111 (0x6f) bits[7:0] = offset to access the indirect byte register 0xa0. offset: 0x36 (bits[15:8], 0x37 (bits[7:0]) location: (001 eee) -> {0x0, off set} -> 0xa0 holds the data. 15 - 0 reserved ro 0x0000 table 4-24: eee global registers (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 99 KSZ8795clx eee global register 4 global eee wakeup error threshold control register reg. 110 (0x6e) bits[7:5 ] = 001 for eee, reg. 110 bits[3:0] = 0 x0 for the indirect global register, reg. 111 (0x6f) bits[7:0] = offset to access the indirect byte register 0xa0. offset: 0x38 (bits[15:8]), 0x39 (bits[7:0]) location: (001 eee) -> {0x0, off set} -> 0xa0 holds the data. 15 - 0 eee wakeup threshold this value specifies the maximum time allowed for phy to wake up. if wakeup time is longer than this, eee wakeup error count will be incremented. note: this is eee stand ard, don t change. ro 0x0201 eee global register 5 global eee pcs diagno stic control register reg. 110 (0x6e) bits[7:5 ] = 001 for eee, reg. 110 bits[3:0] = 0 x0 for the indirect global register, reg. 111 (0x6f) bits[7:0] = offset to access the indirect byte register 0xa0. offset: 0x3a (bits[15:8 ]), 0x3b (bits[7:0]) location: (001 eee) -> {0x0, off set} -> 0xa0 holds the data. 15 - 0 reserved ro 0x0001 table 4-25: eee port registers address name description mode default eee port register 0 port auto-negotiation expansion status register reg. 110 (0x6e) bits[7:5] = 001 for eee, reg. 110 bits[3:0] = 0xn, n = 1-4 for the indirect port register, reg. 111 (0x6f) bits[7:0] = offset to access the indirect byte register 0xa0. offset: 0x0c (bits[15:8 ]), 0x0d (bits[7:0]) location: (001 eee) -> {0xn, offset} -> 0xa0 holds the data. 15 - 7 reserved ro 9h000 6 receive next page loca- tion able 1 = received next page storage location is speci- fied by bits[6:5] 0 = received next page storage location is not specified by bits[6:5] ro 1 5 received next page storage location 1 = link partner next pages are stored in miim register 8h (additional next page) 0 = link partner next pages are stored in miim register 5h ro 1 4 parallel detection fault 1 = a fault has been detected via the parallel detection function. 0 = a fault has not been detected via the parallel detection function. this bit is cleared after reading. r/lh 0 3 link partner next page able 1 = link partner is next page abled 0 = link partner is not next page abled ro 0 2 next page able 1 = local device is next page abled 0 = local device is not next page abled ro 1 1 page received 1 = a new page has been received 0 = a new page has not been received r/lh 0 table 4-24: eee global registers (continued) address name description mode default downloaded from: http:///
KSZ8795clx ds00002112a-page 100 ? 2016 microchip technology inc. 0 link partner auto-negoti- ation able 1 = link partner is auto-negotiation abled 0 = link partner is not auto-negotiation abled ro 0 eee port register 1 port auto-negotiation next page transmit register reg. 110 (0x6e) bits[7 :5] = 001 for eee, reg. 110 bi ts[3:0] = 0xn, n = 1-4 for th e indirect port register , reg. 111 (0x6f) bits[7:0] = offset to access the indirect byte register 0xa0. offset: 0x0e (bits[15:8]), 0x0f (bits[7:0]) location: (001 eee) -> {0xn, offset} -> 0xa0 holds the data. this register doesnt need to be set if eee port register 5 bi t[7] = 1 default for automatically perform eee capability 15 next page next page (np) is used by the next page function to indicate whether or not this is the last next page to be transmitted. np shall be set as follows: 1 = additional next page(s) will follow. 0 = last page. r/w 0 14 reserved ro 0 13 message page message page (mp) is used by the next page function to differentiate a message page from an unformatted page. mp shall be set as follows: 1 = message page 0 = unformatted page r/w 1 12 acknowledge 2 acknowledge 2 (ack2) is used by the next page function to indicate that a device has the ability to comply with the message. a ck2 shall be set as fol- lows: 1 = will comply with message. 0 = cannot comply with message. r/w 0 11 toggle toggle (t) is used by the arbitration function to ensure synchronization with the link partner during next page exchange. this bit shall always take the opposite value of the toggle bit in the previously exchanged link codeword. the initial value of the toggle bit in the first next page transmitted is the inverse of bit[11] in the base link codeword and, therefore, may assume a value of logic one or zero. the toggle bit shall be set as follows: 1 = previous value of the transmitted link code- word equal to logic zero. 0 = previous value of the transmitted link code- word equal to logic one. ro 0 10 - 0 message/ unformatted code field message/unformatted code field bits[10:0] r/w 1 table 4-25: eee port registers (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 101 KSZ8795clx eee port register 2 port auto-negotiation link partner next page receive register reg. 110 (0x6e) bits[7:5] = 001 for eee, reg. 110 bits[3:0] = 0xn, n = 1-4 for the indirect port register, reg. 111 (0x6f) bits[7:0] = offset to access the indirect byte register 0xa0. offset: 0x10 (bits[15:8 ]), 0x11 (bits[7:0]) location: (001 eee) -> {0xn, offset} -> 0xa0 holds the data. 15 next page next page (np) is used by the next page function to indicate whether or not this is the last next page to be transmitted. np shall be set as follows: 1 = additional next page(s) will follow. 0 = last page. ro 0 14 acknowledge acknowledge (ack) is used by the auto-negotiation function to indicate that a device has successfully received its link partners link codeword. the acknowledge bit is encoded in bit d14 regardless of the value of the selector field or link codeword encoding. if no next page information is to be sent, this bit shall be set to logic one in the link code- word after the reception of at least three consecu- tive and consistent flp bursts (ignoring the acknowledge bit value). ro 0 13 message page message page (mp) is used by the next page function to differentiate a message page from an unformatted page. mp shall be set as follows: 1 = message page 0 = unformatted page ro 0 12 acknowledge 2 acknowledge 2 (ack2) is used by the next page function to indicate that a device has the ability to comply with the message. a ck2 shall be set as fol- lows: 1 = will comply with message. 0 = cannot comply with message. ro 0 11 toggle toggle (t) is used by the arbitration function to ensure synchronization with the link partner during next page exchange. this bit shall always take the opposite value of the toggle bit in the previously exchanged link codeword. the initial value of the toggle bit in the first next page transmitted is the inverse of bit[11] in the base link codeword and, therefore, may assume a value of logic one or zero. the toggle bit shall be set as follows: 1 = previous value of the transmitted link code- word equal to logic zero. 0 = previous value of the transmitted link code- word equal to logic one. ro 0 10 - 0 message/ unformatted code field message/unformatted code field bits [10:0] ro 0 table 4-25: eee port registers (continued) address name description mode default downloaded from: http:///
KSZ8795clx ds00002112a-page 102 ? 2016 microchip technology inc. eee port register 3 link partner eee capab ility status and local device eee capability advisement register reg. 110 (0x6e) bits[7:5] = 001 for eee, reg. 110 bits[3:0] = 0xn, n = 1-4 for the indirect port register, reg. 111 (0x6f) bits[7:0] = offset to access the indirect byte register 0xa0. offset: 0x28 (bits[15:8]), 0x29 (bits[7:0]) location: (001 eee) -> {0xn, offset} -> 0xa0 holds the data. 15 reserved ro 0 14 lp 10gbase- kr eee 1 = eee is supported for 10gbase-kr 0 = eee is not supported for 10gbase-kr note: lp = link partner ro 0 13 lp 10gbase- kx4 eee 1 = eee is supported for 10gbase-kx4 0 = eee is not supported for 10gbase-kx4 ro 0 12 lp 1000base- kx eee 1 = eee is supported for 1000base-kx 0 = eee is not supported for 1000base-kx ro 0 11 lp 10gbase-t eee 1 = eee is supported for 10gbase-t 0 = eee is not supported for 10gbase-t ro 0 10 lp 1000base-t eee 1 = eee is supported for 1000base-t 0 = eee is not supported for 1000base-t ro 0 9l p 100base-tx eee 1 = eee is supported for 100base-tx 0 = eee is not supported for 100base-tx ro 0 8 - 2 reserved ro 7h0 1 local 100base-tx eee 1 = eee is supported for 100base-tx 0 = eee is not supported for 100base-tx note: this is for local port to support eee capability r/w 1 0 reserved ro 0 eee port register 4 port eee wake up error count register reg. 110 (0x6e) bits[7:5] = 001 for eee, reg. 110 bits[3:0] = 0xn, n = 1-4 for the indirect port register, reg. 111 (0x6f) bits[7:0] = offset to access the indirect byte register 0xa0. offset: 0x2a (bits[15:8]), 0x2b (bits[ 7:0]) location: (001 eee) -> {0xn, offset} -> 0xa0 holds the data. 15 - 0 eee wakeup error counter this count is incremented by one whenever a wakeup from lpi to idle state is longer than the wake-up error threshold time specified in eee global register 4. the default of wake-up error threshold time is 20.5 s. this register is read- cleared. ro 0x0000 table 4-25: eee port registers (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 103 KSZ8795clx eee port register 5 port eee cont rol register reg. 110 (0x6e) bits[7:5] = 001 for eee, reg. 110 bits[3:0] = 0xn, n = 1-4 for the indirect port register, reg. 111 (0x6f) bits[7:0] = offset to access the indirect byte register 0xa0. offset: 0x2c (bits[15:8]), 0x 2d (bits[7:0]) location: (001 eee) -> {0xn, offset} -> 0xa0 holds the data. 15 10bt eee disable 1 = 10bt eee mode is disabled 0 = 10bt eee mode is enabled note: 10bt eee mode save power by reducing signal amplitude only. r/w 1 14 - 8 reserved ro 7h0 7 h/w based eee np auto-negoti- ation enable 1 = h/w will automatically perform eee capability exchange with link partner through next page exchange. eee 100bt enable (bit[0] of this regis- ter). will be set by h/w if eee capability is matched. 0 = h/w-based eee capabili ty exchange is off. eee capability exchange is done by software. r/w 1 6 h/w 100bt eee enable status 1 = 100bt eee is enabled by h/w-based np exchange 0 = 100bt eee is disabled r0 5t x l p i received 1 = indicates that the transmit pcs has received low power idle signaling one or more times since the register was last read. 0 = indicates that the pc s has not received low power idle signaling. this bit is cleared after reading. r/rc 0 4t x l p i indication 1 = indicates that the tr ansmit pcs is currently receiving low power idle signals. 0 = indicates that the pcs is not currently receiving low power idle signals. r0 3r x l p i received 1 = indicates that the receive pcs has received low power idle signaling one or more times since the register was last read. 0 = indicates that the pc s has not received low power idle signaling. this bit is cleared after reading. r/rc 0 2r x l p i indication 1 = indicates that the re ceive pcs is currently receiving low power idle signals. 0 = indicates that the pcs is not currently receiving low power idle signals. r0 1 eee sw mode enable 1 = eee is enabled through s/w setting bit[0] of this register. 0 = eee is enabled through h/w auto-negotiation r/w 0 0 eee sw 100bt enable 1 = eee 100bt is enabled 0 = eee 100bt is disabled note: this bit could be set by s/w or h/w if h/w- based eee next page auto-negotiation enable is on. r/w 0 table 4-25: eee port registers (continued) address name description mode default downloaded from: http:///
KSZ8795clx ds00002112a-page 104 ? 2016 microchip technology inc. programming examples: read operation 1. use the indirect access control register to select register to be read, to read the eee global register 0 (global eee qm buffer control register). 2. write 0x30 to the register 110 (0x6e) // eee selected and read operation, and 4 msbs of port number = 0 for the global register. 3. write 0x30 to the indirect register 111 (0x6f) // trigger the read operation and ready to read the eee global reg- ister 0 bits[15:8]. 4. read the indirect byte register 160 (0xa0) // get the bits[15:8] value of the eee gl obal register 0. write operation 1. write 0x20 to register 110 (0x6e) // eee selected a nd write operation, 4 msbs of port number = 0 is for global register. 2. write 0x31 to register 111 (0x6f) // select the offset a ddress, ready to write the eee global register 0 bits[7:0]. 3. write new value to the indirect by te register 160 (0xa0) bits[7:0]. 4.10 management information base (mib) counters the mib counters are provided on per port basis. these c ounters are read using indirect memory access as in ta b l e 4 - 26 . eee port register 6 port eee lpi recove ry time register reg. 110 (0x6e) bits[7:5] = 001 for eee, reg. 110 bits[3:0] = 0xn, n = 1-4 for the indirect port register, reg. 111 (0x6f) bits[7:0] = offset to access the indirect byte register 0xa0. offset: 0x2e (bits[15:8]), 0x2f (bits[7:0]) location: (001 eee) -> {0xn, offset} -> 0xa0 holds the data. 15 - 8 reserved ro 1 7 - 0 lpi recovery counter this register specifies the time that the mac device has to wait before it can start to send out packets. this value should be the maximum of the lpi recovery time between lo cal device and remote device. the unit is 640 ns. the default is about 25 s = 39 (0x27) 640 ns note: this value can be adjusted if phy recovery time is less than the standard 20.5 s for the pack- ets to be sent out quickly from eee lpi mode. r/w 0x27 table 4-26: port mib counter indirect memory offsets offset counter na me description 0x0 rxhiprioritybyte rx hi-priority octet count including bad packets. 0x1 rxundersizepkt rx undersize packets w/good crc. 0x2 rxfragments rx fragment packets w/bad crc, symbol errors or alignment errors. 0x3 rxoversize rx oversize packets w/good crc (maximum: 1536 or 1522 bytes). 0x4 rxjabbers rx packets longer than 1 522 bytes w/either crc errors, alignment errors, or symbol errors (depends on max packet size setting) or rx packets longer than 1916 bytes only. 0x5 rxsymbolerror rx packets w/ invalid data symbol and legal preamble, packet size. 0x6 rxcrcerror rx packets within (64,1522) by tes w/an integral number of bytes and a bad crc (upper limit depends on max packet size setting). 0x7 rxalignmenterror rx packets within (64,1522) bytes w/a non-int egral number of bytes and a bad crc (upper limit depends on max packet size setting). table 4-25: eee port registers (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 105 KSZ8795clx 0x8 rxcontrol8808pkts the number of mac control frames received by a port with 88-08h in ethertype field. 0x9 rxpausepkts the number of pause frames received by a port. pause frame is qualified with ethertype (88-08h) , da, control opcode (00-01), data length (64 byte min), and a valid crc. 0xa rxbroadcast rx good broadcast packets (n ot including errored broadcast packets or valid multicast packets). 0xb rxmulticast rx good multicast packets ( not including mac control frames, errored multicast packets or va lid broadcast packets). 0xc rxunicast rx good unicast packets. 0xd rx64octets total rx packets (bad packets included) that were 64 octets in length. 0xe rx65to127octets total rx packets (bad packets included) that are between 65 and 127 octets in length. 0xf rx128to255octets total rx packets (bad packets included) that are between 128 and 255 octets in length. 0x10 rx256to511octets total rx packets (bad packets included) that are between 256 and 511 octets in length. 0x11 rx512to1023octets total rx packets (bad packets included) that are between 512 and 1023 octets in length. 0x12 rx1024to1522octets total rx packets (bad packets included) that are between 1024 and 1522 octets in length. 0x13 rx1523to2000octets total rx packets (bad packets included) that are between 1523 and 2000 octets in length. 0x14 rx2001tomax-1octets total rx packets (bad packets included) that are between 2001 and max-1 octets in length (upper limit depends on max packet size ?1). 0x15 txhiprioritybyte tx hi-priority good octet count, including pause packets. 0x16 txlatecollision the number of times a col lision is detected later than 512 bit-times into the tx of a packet. 0x17 txpausepkts the number of paus e frames transmitted by a port. 0x18 txbroadcastpkts tx good broadcast packets (not including errored broadcast or valid multicast packets). 0x19 txmulticastpkts tx good multicast packets (not including errored multicast packets or valid broadcast packets). 0x1a txunicastpkts tx good unicast packets. 0x1b txdeferred tx packets by a port for which the 1st tx attempt is delayed due to the busy medium. 0x1c txtotalcollision tx total collision, half-duplex only. 0x1d txexcessivecollision a count of frames for which tx fails due to excessive collisions. 0x1e txsinglecollision successful tx frames on a po rt for which tx is inhibited by exactly one collision. 0x1f txmultiplecollision successful tx frames on a port for which tx is inhibited by more than one collision. table 4-26: port mib counter indirect memory offsets (continued) offset counter na me description downloaded from: http:///
KSZ8795clx ds00002112a-page 106 ? 2016 microchip technology inc. table 4-27: format of per-port mib counter address name description mode default for port 2, the base is 0x20, same offset definition (0x20-0x3f) for port 3, the base is 0x40, same offset definition (0x40-0x5f) for port 4, the base is 0x60, same offset definition (0x60-0x7f) for port 5, the base is 0x80, same offset definition (0x80-0x9f) 38 overflow 1 = counter overflow. 0 = no counter overflow. ro 0 37 count valid 1 = counter value is valid. 0 = counter value is not valid. ro 0 36 - 30 reserved ro all 0 29 - 0 counter values counter value ro 0 table 4-28: all port dropped packet mib counters offset counter na me description 0x100 port 1 rx total bytes port 1 rx total octet count, including bad packets. 0x101 port 1 tx total bytes port 1 tx total good octet count, including pause packets. 0x102 port 1 rx drop packets port 1 rx packets dropped due to lack of resources. 0x103 port 1 tx drop packets port 1 tx packets dropped due to lack of resources. 0x104 port 2 rx total bytes port 2 rx total octet count, including bad packets. 0x105 port 2 tx total bytes port 2 tx total good octet count, including pause packets. 0x106 port 2 rx drop packets port 2 rx packets dropped due to lack of resources. 0x107 port 2 tx drop packets port 2 tx packets dropped due to lack of resources. 0x108 port 3 rx total bytes port 3 rx total octet count, including bad packets. 0x109 port 3 tx total bytes port 3 tx total good octet count, including pause packets. 0x10a port 3 rx drop packets port 3 rx pa ckets dropped due to lack of resources. 0x10b port 3 tx drop packets port 3 tx packets dropped due to lack of resources. 0x10c port 4 rx total bytes port 4 rx total octet count, including bad packets. 0x10d port 4 tx total bytes port 4 tx total good octet count, including pause packets. 0x10e port 4 rx drop packets port 4 rx pa ckets dropped due to lack of resources. 0x10f port 4 tx drop packets port 4 tx pa ckets dropped due to lack of resources. 0x110 port 5 rx total bytes port 5 rx total octet count, including bad packets. 0x111 port 5 tx total bytes port 5 tx total good octet count, including pause packets. 0x112 port 5 rx drop packets port 5 rx packets dropped due to lack of resources. 0x113 port 5 tx drop packets port 5 tx packets dropped due to lack of resources. table 4-29: format of per-port rx/tx total bytes mib counte r (in table 4-28) address name description mode default 38 overflow 1 = counter overflow. 0 = no counter overflow. ro 0 37 count valid 1 = counter value is valid. 0 = counter value is not valid. ro 0 36 reserved ro 0 35 - 0 counter values counter value ro 0 downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 107 KSZ8795clx please note that all per-port mib counters are read-clear. KSZ8795clx also offers the statistic control capability by the global register 8 to control mib to flush counter or freeze counter per port. the KSZ8795clx provides a total of 36 mi b counters per port. these counters are used to monitor the port activity for network management and maintenance. these mib counters are read using indirect memory access, per the following examples. 1. mib counter read (read po rt 1 rx64octets counter) write to register 110 with 0x1c (read mib counters selected) write to register 111 with 0xd (trigger the read operation) then: read register 116 (c ounter value [39:32]) // if bit [38] = 1, there was a counter overflow read register 117 (c ounter value [31:24]) read register 118 (c ounter value [23:16]) read register 119 (c ounter value [15:8]) read register 120 (counter value [7:0]) 2. mib counter read (read po rt 2 rx64octets counter) write to register 110 with 0x1c (read mib counter selected) write to register 111 with 0x2d (trigger the read operation) then: read register 116 (c ounter value [39:32]) // if bit[38] = 1, ther e was a counter overflow read register 117 (c ounter value [31:24]) read register 118 (c ounter value [23:16]) read register 119 (c ounter value [15:8]) read register 120 (counter value [7:0]) 3. mib counter read (read port 1 tx drop packets) write to register 110 with 0x1d write to register 111 with 0x03 then: read register 116 (c ounter value [39:32]) // if bit[38] = 1, ther e was a counter overflow read register 119 (c ounter value [15:8]) read register 120 (counter value [7:0]) table 4-30: format of all dropped packet mib counter (in table 4-28) address name description mode default 38 overflow 1 = counter overflow. 0 = no counter overflow. ro 0 37 count valid 1 = counter value is valid. 0 = counter value is not valid. ro 0 36 - 16 reserved ro all 0 15 - 0 counter values counter value ro 0 downloaded from: http:///
KSZ8795clx ds00002112a-page 108 ? 2016 microchip technology inc. to read out all the counters, the best performance over the spi bus is (160+3) 8 20 = 26 s, where there are 160 registers, 3 overhead, 8 clocks per access, at 50 mhz. in the heaviest condition, the byte counter will overflow in 2 min- utes. it is recommended that the software read all the count ers at least every 30 second s. all port mib counters are designed as read clear. 4.11 miim registers all the registers defined in this section can be also accessed via the spi interface. note that different mapping mechanisms are used for miim and spi. the phyad defined in ieee is assigned as 0x1 for port 1, 0x2 for port 2, 0x3 for port 3 and 0x4 for port 4. the regad supported are 0x0-0x5 (0h-5h), 0x1d (1dh) and 0x1f (1fh). table 4-31: miim registers address name description mode default register 0h: basic control 15 soft reset 1 = phy soft reset. 0 = normal operation. r/w (sc) 0 14 loopback 1 = perform mac loopback, loopback path as fol- lows: assume the loopback is at port 1 mac, port 2 is the monitor port. port 1 mac loopback (port 1 reg. 0, bit[14] = 1 start: rxp2/rxm2 (port 2). can also start from port 3, 4, 5 loopback: mac/phy interface of port 1s mac end: txp2/txm2 (port 2). can also end at ports 3, 4, 5 respectively setting address 0x3, 4, 5 reg. 0, bit[14] = 1 will perform mac loopback on ports 3, 4, 5, respec- tively. 0 = normal operation. r/w 0 13 force 100 1 = 100 mbps. 0 = 10 mbps. r/w 1 12 an enable 1 = auto-negotiation enabled. 0 = auto-negotiation disabled. r/w 1 11 power down 1 = power down. 0 = normal operation. r/w 0 10 phy isolate 1 = electrical phy isolation of phy from tx+/tx-. 0 = normal operation. r/w 0 9 restart an 1 = restart auto-negotiation. 0 = normal operation. r/w 0 8 force full duplex 1 = full duplex. 0 = half duplex. r/w 1 7 reserved ro 0 6 reserved ro 0 5 hp_mdix 1 = hp auto-mdi/mdix mode 0 = microchip auto-mdi/mdix mode r/w 1 4 force mdi 1 = mdi mode when disable auto-mdi/mdix. 0 = mdix mode when disable auto-mdi/mdix. r/w 0 3 disable auto mdi/mdi-x 1 = disable auto-mdi/mdix. 0 = enable auto-mdi/mdix. r/w 0 2 disable far end fault 1 = disable far end fault detection. 0 = normal operation. r/w 0 downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 109 KSZ8795clx 1 disable transmit 1 = disable transmit. 0 = normal operation. r/w 0 0 disable led 1 = disable led. 0 = normal operation. r/w 0 register 1h: basic status 15 t4 capable 0 = not 100 baset4 capable. ro 0 14 100 full capable 1 = 100base-tx full-duplex capable. 0 = not capable of 100base-tx full-duplex. ro 1 13 100 half capable 1 = 100base-tx half-duplex capable. 0 = not 100base-tx half-duplex capable. ro 1 12 10 full capable 1 = 10base-t full-duplex capable. 0 = not 10base-t full-duplex capable. ro 1 11 10 half capable 1 = 10base-t half-duplex capable. 0 = 10base-t half-duplex capable. ro 1 10 - 7 reserved ro 0 6 reserved ro 0 5 an complete 1 = auto-negotiation complete. 0 = auto-negotiation not completed. ro 0 4 far end fault 1 = far end fault detected. 0 = no far end fault detected. ro 0 3 an capable 1 = auto-negotiation capable. 0 = not auto-negotiation capable. ro 1 2 link status 1 = link is up. 0 = link is down. ro 0 1 reserved ro 0 0 extended capable 0 = not extended register capable. ro 0 register 2h: phyid high 15 - 0 phyid high high order phyid bits. ro 0x0022 register 3h: phyid low 15 - 0 phyid low low order phyid bits. ro 0x1550 register 4h: advertisement ability 15 reserved ro 0 14 reserved ro 0 13 reserved ro 0 12 - 11 reserved ro 01 10 pause 1 = advertise pause ability. 0 = do not advertise pause ability. r/w 1 9r e s e r v e d r / w 0 8 adv 100 full 1 = advertise 100 full-duplex ability. 0 = do not advertise 100 full-duplex ability. r/w 1 7 adv 100 half 1 = advertise 100 half-duplex ability. 0 = do not advertise 100 half-duplex ability. r/w 1 6 adv 10 full 1 = advertise 10 full-duplex ability. 0 = do not advertise 10 full-duplex ability. r/w 1 5 adv 10 half 1 = advertise 10 half-duplex ability. 0 = do not advertise 10 half-duplex ability. r/w 1 table 4-31: miim registers (continued) address name description mode default downloaded from: http:///
KSZ8795clx ds00002112a-page 110 ? 2016 microchip technology inc. 4 - 0 selector field [00001] = ieee 802.3 ro 00001 register 5h: link partner ability 15 reserved ro 0 14 reserved ro 0 13 reserved ro 0 12 - 11 reserved ro 0 10 pause 1 = link partner flow control capable. 0 = link partner not flow control capable. ro 0 9 reserved ro 0 8 adv 100 full 1 = link partner 100bt full-duplex capable. 0 = link partner not 100bt full-duplex capable. ro 0 7 adv 100 half 1 = link partner 100bt half-duplex capable. 0 = link partner not 100bt half-duplex capable. ro 0 6 adv 10 full 1 = link partner 10bt full-duplex capable. 0 = link partner not 10bt full-duplex capable. ro 0 5 adv 10 half 1 = link partner 10bt half-duplex capable. 0 = link partner not 10bt half-duplex capable. ro 0 4 - 0 reserved ro 00001 register 1dh: linkmd control/status 15 cdt_enable 1 = enable cable diagnostic. after cdt test has completed, this bit will be self-cleared. 0 = indicates cable diagnostic test (if enabled) has completed and the status information is valid for reading. r/w (sc) 0 14 - 13 cdt_result 00 = normal condition 01 = open condition detected in cable 10 = short condition detected in cable 11 = cable diagnostic test has failed ro 00 12 cdt 10m short 1 = less than 10 meter short ro 0 11 - 9 reserved ro 0 8 - 0 cdt_- fault_count distance to the fault, approximately 0.4m cdt_- fault_count[8:0] ro 000000000 register 1fh: phy special control/status 15 - 11 reserved ro 0000000000 10 - 8 port operation mode indication indicate the current state of port operation mode: 000 = reserved 001 = still in auto-negotiation 010 = 10base-t half duplex 011 = 100base-tx half duplex 100 = reserved 101 = 10base-t full duplex 110 = 100base-tx full duplex 111 = phy/mii isolate ro 001 7 - 6 reserved ro 00 5 polrvs 1 = polarity is reversed 0 = polarity is not reversed ro 0 4 mdi-x status 1 = mdi 0 = mdi-x ro 0 table 4-31: miim registers (continued) address name description mode default downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 111 KSZ8795clx 3 force_lnk 1 = force link pass 0 = normal operation r/w 0 2 pwrsave 1 = enable power save 0 = disable power save r/w 0 1 remote loopback 1 = perform remote loopback, loop back path as follows: port 1 (phy id address 0x1 reg. 1fh, bit[1] = 1 start: rxp1/rxm1 (port 1) loopback: pmd/pma of port 1s phy end: txp1/txm1 (port 1) setting phy id address 0x2, 3, 4, 5 reg. 1fh, bit[1] = 1, will perform remote loopback on ports 2, 3, 4, 5. 0 = normal operation. r/w 0 0 reserved ro 0 table 4-31: miim registers (continued) address name description mode default downloaded from: http:///
KSZ8795clx ds00002112a-page 112 ? 2016 microchip technology inc. 5.0 operational characteristics 5.1 absolute maximum ratings* supply voltage (v dd12a , v dd12d ) .............................................................................................................................. ........ C0.5v to +1.8v (v ddat , v ddio ).............................................................................................................................. ............. C0.5v to +4.0v input voltage .................................................................................................................. ........................... C0.5v to +4.0v output voltage................................................................................................................. .......................... C0.5v to +4.0v lead temperature (soldering, 10s) .............................................................................................. ......................... +260c storage temperature (t s ) ................ .................................................................................................. .... C55c to +150c maximum junction temperature ........ ........................................................................................... ........................ +125c esd rating ..................................................................................................................... ...........................................5 kv *exceeding the absolute maximum rating may damage the dev ice. stresses greater than the absolute maximum rating may cause permanent damage to the device. operation of the device at these or any other conditions above those spec- ified in the operating sections of this specification is not implied. maximum conditions for extended periods may affect reliability. 5.2 operating ratings** supply voltage (v dd12a , v dd12d ) .............................................................................................................................. +1.140v to +1.260v (v ddat @ 3.3v)....................................................................................................................... .......... +3.135v to +3.465v (v ddat @ 2.5v)....................................................................................................................... .......... +2.375v to +2.625v (v ddio @ 3.3v) ....................................................................................................................... .......... +3.135v to +3.465v (v ddio @ 2.5v) ....................................................................................................................... .......... +2.375v to +2.625v (v ddio @ 1.8v) ....................................................................................................................... .......... +1.710v to +1.890v ambient temperature (t a ) commercial ..................................................................................................................... .............................0c to +70c industrial..................................................................................................................... .............................. C40c to +85c package thermal resistance ( ja , note 5-1 ) .............................................................................................. +55.05c/w package thermal resistance ( jc , note 5-1 ).............................................................................................. +25.06c/w **the device is not guaranteed to function outside its operatin g ratings. unused inputs must always be tied to an appro- priate logic voltage level (gnd or v dd ). note 5-1 no heat spreader in package. the thermal junction-to-ambient ( ja ) and the thermal junction-to-case ( jc ) are under air velocity 0m/s. note: do not drive input signals without power supplied to the device. downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 113 KSZ8795clx 6.0 electrical characteristics v in = 1.2v/3.3v (typical); t a = +25c. specification is for packaged produc t only. there is no additional transformer con- sumption due to use on chip terminati on technology with internal biasing fo r 10base-t and 100base-tx. the test con- dition is in port 5 rgmii mode (default). measurements were taken with operating ratings. table 6-1: electrical characteristics parameters symbol min. typ. max. units note 100base-tx operation - all ports 100% utilization 100base-tx (transmitter) 3.3v analog i dx 1 4 2 ma v ddat 100base-tx 1.2v i d12 3 5 v dd12a + v dd12d 100base-tx (digital io) 3.3v digital i ddio 1 5 v ddio 10base-t operation - all ports 100% utilization 10base-t (transmitter) 3.3v analog i dx 1 3 5 ma v ddat 10base-t 1.2v i d12 3 0 v dd12a + v dd12d 10base-t (digital io) 3.3v digital i ddio 1 4 v ddio auto-negotiation mode 3.3v analog i dx 6 6 ma v ddat 1.2v analog/digital i d12 3 5 v dd12a + v dd12d 3.3v digital i/o i ddio 1 4 v ddio power management mode soft power-down mode 3.3v i spdm1 0 . 0 7 ma v ddat + v ddio soft power-down mode 1.2v i spdm2 0 . 2 v dd12a + v dd12d energy detect mode (edpd) 3.3v i edm1 2 1 v ddat + v ddio energy detect mode (edpd) 1.2v i edm2 2 6 . 5 v dd12a + v dd12d 100bt eee mode at idle 3.3v i eee1 2 2 . 5 v ddat + v ddio 100bt eee mode at idle 1.2v i eee2 2 7 v dd12a + v dd12d cmos input input high voltage v ih 2.0 v v ddio = 3.3v 1.8 v ddio = 2.5v 1.3 v ddio = 1.8v input low voltage v il 0 . 8 v v ddio = 3.3v 0 . 7 v ddio = 2.5v 0 . 5 v ddio = 1.8v input current (excluding pull-up/pull-down) i in 10 a v in = gnd ~ v ddio cmos outputs output high voltage v oh 2.4 v v ddio = 3.3v 2.0 v ddio = 2.5v 1.5 v ddio = 1.8v downloaded from: http:///
KSZ8795clx ds00002112a-page 114 ? 2016 microchip technology inc. output low voltage v ol 0 . 4 v v ddio = 3.3v 0 . 4 v ddio = 2.5v 0 . 3 v ddio = 1.8v output tri-state leakage i oz 10 a v in = gnd ~ v ddio 100base-tx transmit (measured differentially after 1:1 transformer) peak differential output voltage v o 0.95 1.05 v 100 ? termination on the differential output output voltage imbalance v imb 2 % 100 ? termination on the differential output rise/fall time t r /t f 35 ns rise/fall time imbalance 0 0.5 duty cycle distortion 0.5 ns overshoot 5 % output jitters 0 0.75 1.4 ns peak-to-peak 10base-t receive squelch threshold v sq 300 400 585 mv 5 mhz square wave 10base-t transmit (measured differentially after 1:1 transformer) v ddat = 3.3v peak differential output voltage v p 2.2 2.5 2.8 v 100 ? termination on the differential output output jitters 1.4 3.5 ns peak-to-peak rise/fall times 28 30 ns i/o pin internal pull-up and pull-down resistance i/o pin effective pull-up resistance r 1.8pu 75 95 135 k ? v ddio = 1.8v i/o pin effect ive pull-down resistance r 1.8pd 53 68 120 v ddio = 1.8v i/o pin effective pull-up resistance r 2.5pu 46 60 93 v ddio = 2.5v i/o pin effect ive pull-down resistance r 2.5pd 46 59 103 v ddio = 2.5v i/o pin effective pull-up resistance r 3.3pu 35 45 65 v ddio = 3.3v i/o pin effect ive pull-down resistance r 3.3pd 37 46 74 v ddio = 3.3v table 6-1: electrical characteristics (continued) parameters symbol min. typ. max. units note downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 115 KSZ8795clx 7.0 timing diagrams figure 7-1: gmii signals timing diagram table 7-1: gmii timing parameters symbol parameter min. typ. max. units clock cycle 8 ns t is set-up time 1.2 t ih hold time 1.2 t od output delay respect to clock falling edge 1 downloaded from: http:///
KSZ8795clx ds00002112a-page 116 ? 2016 microchip technology inc. figure 7-2: rgmii v2.0 specification note 7-1 rgmii v2.0 add internal delay (rgmii-id) option to match the data to clock output/input skew for rgmii transmit and receiving, see t he register 86 bits[4:3] for detail. note 7-2 for 10 mbps and 100 mbps. tcyc will scale to 400 ns 40 ns and 40 ns 4 ns. table 7-2: rgmii timing parameters symbol parameter m in. typ. max. units tskewt data to clock outp ut skew (at transmitter) ( note 7-1 ) C500 0 500 ps tskewr data to clock input skew (at receiver) ( note 7-1 )1 2 . 6 ns tsetupt data to clock output setup (at transmitter C integrated delay) 1.0 2.0 tholdt clock to data output hold (at tr ansmitter C integrated delay) 1.0 2.0 tsetupr data to clock input setup (at receiver C integrated delay) 0.8 2.0 tholdr clock to data input hold (at receiver C integrated delay) 0.8 2.0 tcyc clock cycle duration ( note 7-2 ) 7.2 8.0 8.8 duty_g duty cycle for gigabit 45 50 55 % duty_t duty cycle for 10/100t 40 50 60 t r /t f rise/fall time (20-80%) 0.75 ns txc (source of data) txd[8:5][3:0]txd[7:4][3:0] tx_ctl txc (at receiver) txd[3:0] txd[4] txen txd[8:5]txd[7:4] txd[9 txerr txc (with internal delay added) tsetupt tsetupr tholdt tholdr rxc (source of data) rxd[8:5][3:0]rxd[7:4][3:0] rx_ctl rxc (at receiver) rxd[3:0] rxd[4] rxdv rxd[8:5]rxd[7:4] rxd[9 rxerr rxc (with internal delay added) tsetupt tsetupr tholdt tholdr downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 117 KSZ8795clx figure 7-3: mac mode mii timing - data received from mii figure 7-4: mac mode mii timing - data transmitted from mii table 7-3: mac mode mii timing parameters symbol parameter 10base-t/100base-tx min. typ. max. units t cyc3 clock cycle 400/ 40 ns t s3 set-up time 2 t h3 hold time 2 t ov3 output valid 3 8 10 receive timing transmit timing downloaded from: http:///
KSZ8795clx ds00002112a-page 118 ? 2016 microchip technology inc. figure 7-5: phy mode mii timi ng - data received from mii figure 7-6: phy mode mii timi ng - data transmitted from mii table 7-4: phy mode mii timing parameters symbol parameter 10baset/100baset min. typ. max. units t cyc4 clock cycle 400/40 ns t s4 set-up time 10 t h4 hold time 0 t ov4 output valid 16 20 25 receive timing transmit timing downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 119 KSZ8795clx figure 7-7: rmii timing - data received from rmii figure 7-8: rmii timing - data transmitted from rmii table 7-5: rmii timing parameters symbol parameter m in. typ. max. units t cyc clock cycle 20 ns t 1 set-up time 4 t 2 hold time 2 t od output delay 3 10 t cyc t 1 t 2 transmit timing refclk tx_entxd[1:0] t cyc receive timing refclk crsdvrxd[1:0] t od downloaded from: http:///
KSZ8795clx ds00002112a-page 120 ? 2016 microchip technology inc. figure 7-9: spi input timing table 7-6: spi input timing parameters symbol parameter m in. typ. max. units f c clock frequency 50 mhz t chsl spis_n inactive hold time 2 ns t slch spis_n active set-up time 4 t chsh spis_n active hold time 2 t shch spis_n inactive set-up time 4 t shsl spis_n deselect time 10 t dvch data input set-up time 4 t chdx data input hold time 2 t clch clock rise time 1 s t chcl clock fall time 1 t dldh data input rise time 1 t dhdl data input fall time 1 high impedance spis_n spicspid spiq t shsl t shch t chdl t clch t chdx t chsh t slch t chsl t dvch msb lsb t dldh t dhdl downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 121 KSZ8795clx figure 7-10: spi output timing table 7-7: spi output timing parameters symbol parameter m in. typ. max. units f c clock frequency 50 mhz t clqx spiq hold time 0 0 ns t clqv clock to low spiq valid 60 t ch clock high time 9 t cl clock low time 9 t qlqh spiq rise time 50 t qhql spiq fall time 50 t shqz spiq disable time 15 t clqx t clqv spis_n spic spiq spid t qlqh t qhql t ch t cl t shqz downloaded from: http:///
KSZ8795clx ds00002112a-page 122 ? 2016 microchip technology inc. figure 7-11: auto- negotiation timing table 7-8: auto-negotiation timing parameters symbol parameter m in. typ. max. units t btb flp burst to flp burst 8 16 24 ms t flpw flp burst width 2 t pw clock/data pulse width 100 ns t ctd clock pulse to data pulse 55.5 64 69.5 s t ctc clock pulse to clock pulse 111 128 139 number of clock/data pulses per burst 17 33 flpburst flpburst tx+/tx?tx+/tx? t flpw t btb clockpulse data pulse clockpulse data pulse t pw t ctd t ctc t pw downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 123 KSZ8795clx figure 7-12: mdc/mdio timing table 7-9: mdc/mdio typical timing parameters symbol parameter min. typ. max. units f c clock frequency 2.5 25 mhz t p mdc period 400 ns t md1 mdio (phy input) set-up to rising edge of mdc 10 t md2 mdio (phy input) hold from rising edge of mdc 4 t md3 mdio (phy output) delay from rising edge of mdc 5 222 t md1 valid data mdio (phy input) valid data mdc t md2 mdio (phy output) valid data t md3 t p downloaded from: http:///
KSZ8795clx ds00002112a-page 124 ? 2016 microchip technology inc. figure 7-13: power-down/power-up and reset timing table 7-10: reset timing parameters symbol parameter m in. typ. max. units t sr stable supply voltages to reset high 10 ms t cs configuration set-up time 5 ns t ch configuration hold time 5 t rc reset to strap-in pin output 6 t vr 3.3v rise time 200 s supply voltage rst# strap-in value strap-in/output pin t vr t sr t cs t ch t rc downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 125 KSZ8795clx 8.0 reset circuit the following discrete reset circuit, shown in figure 8-1 , is recommended when powering up the KSZ8795 device. for an application where the reset circuit signal comes from another device (e.g., cpu, fpga, etc.), the reset circuit as shown in figure 8-2 is recommended. figure 8-1: recommended reset circuit figure 8-2: recommended circuit for interfacing with cpu/fpga reset figure 8-2 shows a reset circuit recommended for applications w here reset is driven by another device (for example, the cpu or an fpga). the reset out rst_out_n from cp u/fpga provides the warm reset after power up reset. d2 is required if using different v ddio voltage between switch and cpu/fpga. dio de d2 should be selected to provide maximum 0.3v vf (forward voltage), for example, vishay bat54, mss1p2l. alternatively, a level shifter device can also be used. d2 is not required if switch and cpu/fpga use same v ddio voltage. r 10k c 10f d1 ks8795 rst d1: 1n4148 vddio r10k d2 c 10f d1 cpu/fpga rst_out_n ks8795 rst d1, d2: 1n4148 vddio downloaded from: http:///
KSZ8795clx ds00002112a-page 126 ? 2016 microchip technology inc. 9.0 selection of isolation transformer one simple 1:1 isolation transformer is needed at the line in terface. an isolation tran sformer with integrated common- mode choke is recommended for exceeding fcc requirements at line side. request to separate the center taps of rx/ tx at chip side. the ieee 80 2.3u standard for 100base-tx assumes a transformer loss of 0.5 db. for the transmit line transformer, insertion loss of up to 1.3 db can be compensa ted by increasing the line drive current by means of reducing the iset resi stor value. ta b l e 9 - 1 gives recommended transformer characteristics. table 9-2 lists the transformer vendors that provide compatible magnetic parts for this device. 10.0 selection of reference crystal table 10-1 lists the typical reference crysta l characteristics for this device. note 10-1 typical value varies per specific crystal specs. table 9-1: 25 mhz crystal/refer ence clock selec tion criteria characteristics value test condition turns ratio 1 ct : 1 ct open-circuit inductance (min.) 350 h 100 mv, 100 khz, 8 ma insertion loss (max.) 1.1 db 0.1 mhz to 100 mhz hipot (min.) 1500 v rms table 9-2: qualified magnetic vendors vendors and parts auto mdix number of ports vendors and parts auto mdix number of ports pulse h1164nl yes 4 pulse h1102 yes 1 ycl ph406082 yes 4 bel fuse s558-5999- u7 yes 1 tdk tla-6t718a yes 1 ycl pt163020 yes 1 lankom lf-h41s yes 1 transpower hb726 yes 1 datatronic nt79075 yes 1 delta lf8505 yes 1 table 10-1: typical reference crystal characteristics characteristics value frequency 25.00000 mhz frequency tolerance (max.) 50 ppm load capacitance (max.) ( note 10-1 ) 27 pf series resistance (max. esr) 40 ? downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 127 KSZ8795clx 11.0 package outlines note: for the most current package drawings, please se e the microchip packaging specification located at http://www.microchip.com/packaging figure 11-1: 80-lead 10 mm x 10 mm lqfp downloaded from: http:///
KSZ8795clx ds00002112a-page 128 ? 2016 microchip technology inc. appendix a: data sheet revision history table a-1: revision history revision section/figure/entry correction ds00002112a (03-28-16) converted micrel data sheet KSZ8795clx to microchip ds00002112a. minor text changes throughout. registers updated various port register descriptions. gmii and rgmii diagrams updated images and associated table parameters. downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 129 KSZ8795clx the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site con- tains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), te chnical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of semi- nars and events, listings of microchip sales offi ces, distributors and factory representatives customer change notification service microchips customer notification service helps keep customers current on microc hip products. subscribers will receive e-mail notification whenever there are changes, updates, revisi ons or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under support, click on customer change notifi- cation and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this docu- ment. technical support is available through the web site at: http://microchip.com/support downloaded from: http:///
KSZ8795clx ds00002112a-page 130 ? 2016 microchip technology inc. product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: KSZ8795 - integrated 5-port, 10/100 managed ethernet switch with gigabit gmii/rgmii and mii/rmii interfaces interface: c = configurable package: l = 80-pin lqfp special attribute: x = none temperature: c = 0 ? c to +70 ? c (commercial) i = C40 ? c to +85 ? c (industrial) bond wire: c = copper examples: a) KSZ8795clxcc configurable interface 80-pin lqfp commercial temperature copper wire bonding b) KSZ8795clxic configurable interface 80-pin lqfp industrial temperature copper wire bonding part no. x x package interface device x temperature x bond wire x special attribute downloaded from: http:///
? 2016 microchip technology inc. ds00002112a-page 131 information contained in this publication regarding device applications and the like is provided on ly for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with yo ur specifications. microchip make s no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fi tness for purpose . microchip disclaims all liability arising from this information and its use. use of micro- chip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, impl icitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip l ogo, anyrate, dspic, flashflex, flexpwr, heldo, jukeblox, keeloq, keeloq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersyn ch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, body com, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit se rial programming, icsp, inter-c hip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, re al ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, ts harc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of mi crochip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchi p technology incorporated in the u.s.a. silicon storage technology is a regi stered trademark of microchip tech nology inc. in other countries. gestic is a registered trademarks of microc hip technology germany ii gmbh & co. kg, a s ubsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-5224-0430-9 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchips c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchips quality system for the design and manufacture of development syst ems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:///
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